Copper plating process for through silicon via with high aspect ratio in advanced packaging

Yu Hung Huang, Huei-Huang Lee, Sheng-Jye Hwang, Durn Yuan Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Through silicon via (TSV) is a technology which allows devices to be connected three-dimensionally. Three dimensional vertical integration using TSV Cu interconnect can greatly increase the packaging density and is one of the most advanced and promising technologies for future IC packaging. However, Cu filling of void free through silicon via with high aspect ratio (AR≥10) has been a challenge for a long time. In this paper, successful fabrication of void free TSV with very high aspect ratio was demonstrated via electroplating process. Proper equipment and processing conditions for electroplating are required. The same equipment and similar chemicals and process conditions could also be applied to fabricate high quality redistribution line technology (RDL).

Original languageEnglish
Title of host publicationProceedings of the ASME InterPack Conference 2009, IPACK2009
Pages9-14
Number of pages6
DOIs
Publication statusPublished - 2010 Jun 25
Event2009 ASME InterPack Conference, IPACK2009 - San Francisco, CA, United States
Duration: 2009 Jul 192009 Jul 23

Publication series

NameProceedings of the ASME InterPack Conference 2009, IPACK2009
Volume1

Other

Other2009 ASME InterPack Conference, IPACK2009
CountryUnited States
CitySan Francisco, CA
Period09-07-1909-07-23

Fingerprint

Copper plating
Aspect ratio
Packaging
Silicon
Electroplating
Fabrication
Processing

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Huang, Y. H., Lee, H-H., Hwang, S-J., & Huang, D. Y. (2010). Copper plating process for through silicon via with high aspect ratio in advanced packaging. In Proceedings of the ASME InterPack Conference 2009, IPACK2009 (pp. 9-14). (Proceedings of the ASME InterPack Conference 2009, IPACK2009; Vol. 1). https://doi.org/10.1115/InterPACK2009-89163
Huang, Yu Hung ; Lee, Huei-Huang ; Hwang, Sheng-Jye ; Huang, Durn Yuan. / Copper plating process for through silicon via with high aspect ratio in advanced packaging. Proceedings of the ASME InterPack Conference 2009, IPACK2009. 2010. pp. 9-14 (Proceedings of the ASME InterPack Conference 2009, IPACK2009).
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abstract = "Through silicon via (TSV) is a technology which allows devices to be connected three-dimensionally. Three dimensional vertical integration using TSV Cu interconnect can greatly increase the packaging density and is one of the most advanced and promising technologies for future IC packaging. However, Cu filling of void free through silicon via with high aspect ratio (AR≥10) has been a challenge for a long time. In this paper, successful fabrication of void free TSV with very high aspect ratio was demonstrated via electroplating process. Proper equipment and processing conditions for electroplating are required. The same equipment and similar chemicals and process conditions could also be applied to fabricate high quality redistribution line technology (RDL).",
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Huang, YH, Lee, H-H, Hwang, S-J & Huang, DY 2010, Copper plating process for through silicon via with high aspect ratio in advanced packaging. in Proceedings of the ASME InterPack Conference 2009, IPACK2009. Proceedings of the ASME InterPack Conference 2009, IPACK2009, vol. 1, pp. 9-14, 2009 ASME InterPack Conference, IPACK2009, San Francisco, CA, United States, 09-07-19. https://doi.org/10.1115/InterPACK2009-89163

Copper plating process for through silicon via with high aspect ratio in advanced packaging. / Huang, Yu Hung; Lee, Huei-Huang; Hwang, Sheng-Jye; Huang, Durn Yuan.

Proceedings of the ASME InterPack Conference 2009, IPACK2009. 2010. p. 9-14 (Proceedings of the ASME InterPack Conference 2009, IPACK2009; Vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Huang YH, Lee H-H, Hwang S-J, Huang DY. Copper plating process for through silicon via with high aspect ratio in advanced packaging. In Proceedings of the ASME InterPack Conference 2009, IPACK2009. 2010. p. 9-14. (Proceedings of the ASME InterPack Conference 2009, IPACK2009). https://doi.org/10.1115/InterPACK2009-89163