Counter-based output selection for test response compaction

Wei Cheng Lien, Kuen-Jong Lee, Tong Yu Hsieh, Krishnendu Chakrabarty, Yu Hua Wu

Research output: Contribution to journalArticlepeer-review

7 Citations (Scopus)


Output selection is a recently proposed test response compaction method, where only a subset of output response bits is selected for observation. It can achieve zero aliasing, full X-tolerance, and high diagnosability. One critical issue for output selection is how to implement the selection hardware. In this paper, we present a counter-based output selection scheme that employs only a counter and a multiplexer, hence involving very small area overhead and simple test control. The proposed scheme is ATPG-independent and thus can easily be incorporated into a typical design flow. Two efficient output selection algorithms are presented to determine the desired output responses, one using a single counter operation for simpler test control and the other using more counter operations for achieving a better test-response reduction ratio. Experimental results show that for stuck-at faults in large ISCAS'89 and ITC'99 benchmark circuits, 48%-90% reduction ratios on test responses can be achieved with only one counter and one multiplexer employed. Even better results, i.e., 76%-95% reductions, can be obtained for transition faults. It is also shown that the diagnostic resolution of this method is almost the same as that achieved by observing all output responses.

Original languageEnglish
Article number6387700
Pages (from-to)152-164
Number of pages13
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number1
Publication statusPublished - 2013 Jan 7

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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