Counterdoped pocket thickness optimization of gate-on-source-only tunnel FETs

The optimized tunnel field-effect transistor with a gate electrode overlapping the source region exhibits a steeper subthreshold swing (SS) and a higher on-state tunneling current than the transistor with a gate on the channel only. In the presence of a counterdoped pocket in the source region underneath the gate electrode, the vertical tunneling component dominates over the unwanted lateral tunneling component, and the performance variability is reduced compared to its no-pocket configuration. The optimal pocket thickness, which is a tradeoff between realistic gate work function and the desired SS, is dependent on the bandgap, electron or hole effective mass, permittivity, and tunneling orientation of semiconductor materials, as analyzed in detail in this paper. A numerical procedure is provided to determine the optimal pocket thickness for arbitrary semiconductor materials.