TY - GEN
T1 - Current-aware scheduling for flash storage devices
AU - Huang, Tzu Jung
AU - Ho, Chien Chung
AU - Huang, Po Chun
AU - Chang, Yuan Hao
AU - Chang, Che Wei
AU - Kuo, Tei Wei
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014/9/25
Y1 - 2014/9/25
N2 - As NAND flash memory has become a major choice of storage media in diversified computing environments, the performance issue of flash memory has been extensively addressed in many excellent designs. Among them, an effective strategy is to adopt multiple channels and flash-memory chips to improve the performance on data accesses. However, the degree of data access parallelism cannot be increased by simply increasing the number of channels and chips in the storage device, because it is seriously limited by the maximum current constraint of the bus interface and affected by the access patterns of user data. As a consequence, to maximize the degree of access parallelism, it is of paramount significance to have a proper scheduling strategy to determine the order that read/write requests are served. In this paper, a current-aware scheduling strategy for read/write requests is proposed to maximize the read performance without violating the bus current constraint and without missing (the deadline of) written data. The proposed strategy is then evaluated through a series of experiments, in which the results are quite encouraging.
AB - As NAND flash memory has become a major choice of storage media in diversified computing environments, the performance issue of flash memory has been extensively addressed in many excellent designs. Among them, an effective strategy is to adopt multiple channels and flash-memory chips to improve the performance on data accesses. However, the degree of data access parallelism cannot be increased by simply increasing the number of channels and chips in the storage device, because it is seriously limited by the maximum current constraint of the bus interface and affected by the access patterns of user data. As a consequence, to maximize the degree of access parallelism, it is of paramount significance to have a proper scheduling strategy to determine the order that read/write requests are served. In this paper, a current-aware scheduling strategy for read/write requests is proposed to maximize the read performance without violating the bus current constraint and without missing (the deadline of) written data. The proposed strategy is then evaluated through a series of experiments, in which the results are quite encouraging.
UR - http://www.scopus.com/inward/record.url?scp=84908636734&partnerID=8YFLogxK
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U2 - 10.1109/RTCSA.2014.6910534
DO - 10.1109/RTCSA.2014.6910534
M3 - Conference contribution
AN - SCOPUS:84908636734
T3 - RTCSA 2014 - 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
BT - RTCSA 2014 - 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2014
Y2 - 20 August 2014 through 22 August 2014
ER -