Current density aware power switch placement algorithm for power gating designs

Jai Ming Lin, Che Chun Lin, Zong Wei Syu, Chih Chung Tsai, Kevin Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Due to advances in manufacture technology, leakage current increases dramatically in modern ICs. Power gating technique is an efficient and effective method to resolve this problem. In order to turn off supply voltage in a low-power domain, it has to insert power switches into designs. However, chip area and IR-drop of circuits are impacted by the number and locations of inserted power switches. Unlike previous works using greedy algorithm to handle this problem, this paper proposes a simple model to approximate the equivalent resistance of power switches in a low-power domain, and uses the binary search method to get the precise value. Based on this value, power switches are allocated by a partition-based approach. Experimental results demonstrate that our approach can insert less number of power switches and still satisfy the IR-drop constraint than other approaches. Moreover, this method is very efficient.

Original languageEnglish
Title of host publicationISPD 2014 - Proceedings of the 2014 ACM International Symposium on Physical Design
PublisherAssociation for Computing Machinery
Pages85-92
Number of pages8
ISBN (Print)9781450325929
DOIs
Publication statusPublished - 2014 Jan 1
Event2014 ACM International Symposium on Physical Design, ISPD 2014 - Petaluma, CA, United States
Duration: 2014 Mar 302014 Apr 2

Publication series

NameProceedings of the International Symposium on Physical Design

Other

Other2014 ACM International Symposium on Physical Design, ISPD 2014
CountryUnited States
CityPetaluma, CA
Period14-03-3014-04-02

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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