Abstract
The issue of cycle time reduction and its impact on a company's competitive edge has been gaining considerable attention recently. Generally speaking, shorter cycle times result in better customer satisfaction, lower work-in-process (WIP), higher yield, and better capacity given tool inventory and facility constraints. This paper provides a brief review of key concepts related to cycle time and describes a methodology for cycle time reduction projects in semiconductor wafer fabrication facilities, including the critically important implementation road map step. Finally, a case study is presented to illustrate the effectiveness and potential gains of the proposed cycle time reduction methodology.
| Original language | English |
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| Pages | 418-423 |
| Number of pages | 6 |
| Publication status | Published - 1997 Dec 1 |
| Event | Proceedings of the 1997 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop - Cambridge, MA, USA Duration: 1997 Sept 10 → 1997 Sept 12 |
Other
| Other | Proceedings of the 1997 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop |
|---|---|
| City | Cambridge, MA, USA |
| Period | 97-09-10 → 97-09-12 |
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Engineering(all)
- Industrial and Manufacturing Engineering
- Electrical and Electronic Engineering