DC pulse hot-carrier-stress effects on gate-induced drain leakage current in n-channel MOSFETs

Ja Hao Chen, Shyh Chyi Wong, Yeong Her Wang

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)

Abstract

The dc pulse hot-carrier-stress effects on the degradation in gate-induced drain leakage (GIDL) current in a high field regime and the mechanisms of stress-induced degradation are studied. In this paper, we investigate de pulse stress parameters in GIDL which include frequency, rise/fall time, and amplitude of stressing pulse. The contribution of hot-hole injection, interface state generation, and hot-electron injection in a period of transient stress are identified. It is found that the device degradation increases with increased pulse frequency under maximum gate current stress, while it decreases with reduced pulse frequency under maximum substrate current stress. This work is useful for dc pulse hot-carrier-stress reliability analysis under circuit operation.

Original languageEnglish
Pages (from-to)2746-2753
Number of pages8
JournalIEEE Transactions on Electron Devices
Volume48
Issue number12
DOIs
Publication statusPublished - 2001 Dec

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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