DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET

Fei Gao, Ting Jung Chang, Ang Li, Marcelo Orenes-Vera, Davide Giri, Paul J. Jackson, August Ning, Georgios Tziantzioulis, Joseph Zuckerman, Jinzheng Tu, Kaifeng Xu, Grigory Chirkov, Gabriele Tombesi, Jonathan Balkind, Margaret Martonosi, Luca Carloni, David Wentzlaff

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

As Moore's Law is coming to an end, heterogeneous SoCs have become ubiquitous, improving performance and efficiency with specialized hardware. However, the addition of hardware accelerators makes data supply more challenging. Feeding data to accelerators becomes a bottleneck, especially for data-intensive workloads such as graph analytics, sparse linear algebra, and machine learning applications. DECADES addresses this issue with a combination of accelerators, embedded FPGA (eFPGA), and its unique ''intelligent storage'' (IS) tile. DECADES is one of the largest chips ever built in academia and has the highest core count of cache-coherent, OS-capable, 64-bit RISC-V processors.

Original languageEnglish
Title of host publication2023 IEEE Custom Integrated Circuits Conference, CICC 2023 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350399486
DOIs
Publication statusPublished - 2023
Event44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023 - San Antonio, United States
Duration: 2023 Apr 232023 Apr 26

Publication series

NameProceedings of the Custom Integrated Circuits Conference
Volume2023-April
ISSN (Print)0886-5930

Conference

Conference44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023
Country/TerritoryUnited States
CitySan Antonio
Period23-04-2323-04-26

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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