Defect oriented fault analysis for SRAM

Rei Fu Huang, Yung Fa Chou, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Citations (Scopus)

Abstract

Fault analysis is an important step in establishing detailed fault models or subsequent diagnostics and debugging of a semiconductor memory product. We have performed defect injection in the memory cell array of an industrial SRAM circuit and analyzed the faulty behavior with respect to each defect injected. We found that although some of the defects can be mapped to existing fault models, there are many defects that result in unmodeled faults. Moreover, a defect may exhibit a different faulty behavior at a different location in the cell array. The voltage and temperature parameters can also change the faulty behavior. The simulation results show that almost all open and short defects lead to stuck-at faults, transition faults, and data retention faults.

Original languageEnglish
Title of host publicationProceedings - 12th Asian Test Symposium, ATS 2003
PublisherIEEE Computer Society
Pages256-261
Number of pages6
ISBN (Electronic)0769519512
DOIs
Publication statusPublished - 2003 Jan 1
Event12th Asian Test Symposium, ATS 2003 - Xi'an, China
Duration: 2003 Nov 162003 Nov 19

Publication series

NameProceedings of the Asian Test Symposium
Volume2003-January
ISSN (Print)1081-7735

Other

Other12th Asian Test Symposium, ATS 2003
CountryChina
CityXi'an
Period03-11-1603-11-19

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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