Delay defect coverage for FPGA test configurations based on statistical evaluation

Hsiang Chieh Liao, Jing Jia Liou, Yen Lin Peng, Chih Tsun Huang, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Testing for performance problems of FPGAs has become an important task for ever-increasingly advanced technology. To develop effective testing methodologies, a tool to independently evaluate the quality of test configurations is therefore much needed. In this paper, we present a method to calculate coverages of randomly distributed multiple delay defects in FPGAs. The evaluation algorithm can also identify target paths which are not covered in the current configurations, but can contribute to the quality of the tests. It is shown that the reported metrics can be used to quantify the coverage of delay defects and also further improve high-quality test configurations.

Original languageEnglish
Title of host publication2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Pages216-219
Number of pages4
DOIs
Publication statusPublished - 2005 Dec 1
Event2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) - Hsinchu, Taiwan
Duration: 2005 Apr 272005 Apr 29

Publication series

Name2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Volume2005

Other

Other2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
CountryTaiwan
CityHsinchu
Period05-04-2705-04-29

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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