Demonstration of a novel multilevel storage scheme for phase change memory using a parameterized HSPICE model

D. S. Chao, C. H. Lien, Y. B. Liao, M. H. Chiang, P. H. Yen, M. J. Chen, P. C. Chiang, M. J. Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A novel scheme for PCM multilevel storage, namely the stacked PCM, was proposed in this study. Multiple PCM cells having various programmed volumes are vertically stacked and connected in series to constitute the architecture of the stacked PCM. To simulate the coupling programming characteristics of the stacked PCM, a parameterized PCM HSPICE model was established on the basis of the specific device parameters extracted from the fabricated double confined cells. The results indicate that 2 bits/cell storage can be accomplished by the stacked PCM with three interconnected cells. The simulated step-like R-I curves demonstrate the desirable attributes of direct overwrite capability and larger programming margin. The phenomena of multiple snapbacks can also be observed from the simulated I-V characteristics. Relying on the simulated results by the PCM HSPICE model, the stacked PCM could be one feasible approach for accomplishing multilevel storage in PCM.

Original languageEnglish
Title of host publicationChina Semiconductor Technology International Conference 2012, CSTIC 2012
Pages1303-1310
Number of pages8
Edition1
DOIs
Publication statusPublished - 2012 Dec 1
EventChina Semiconductor Technology International Conference 2012, CSTIC 2012 - Shanghai, China
Duration: 2012 Mar 182012 Mar 19

Publication series

NameECS Transactions
Number1
Volume44
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

OtherChina Semiconductor Technology International Conference 2012, CSTIC 2012
CountryChina
CityShanghai
Period12-03-1812-03-19

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Chao, D. S., Lien, C. H., Liao, Y. B., Chiang, M. H., Yen, P. H., Chen, M. J., Chiang, P. C., & Tsai, M. J. (2012). Demonstration of a novel multilevel storage scheme for phase change memory using a parameterized HSPICE model. In China Semiconductor Technology International Conference 2012, CSTIC 2012 (1 ed., pp. 1303-1310). (ECS Transactions; Vol. 44, No. 1). https://doi.org/10.1149/1.3694464