A novel scheme for PCM multilevel storage, namely the stacked PCM, was proposed in this study. Multiple PCM cells having various programmed volumes are vertically stacked and connected in series to constitute the architecture of the stacked PCM. To simulate the coupling programming characteristics of the stacked PCM, a parameterized PCM HSPICE model was established on the basis of the specific device parameters extracted from the fabricated double confined cells. The results indicate that 2 bits/cell storage can be accomplished by the stacked PCM with three interconnected cells. The simulated step-like R-I curves demonstrate the desirable attributes of direct overwrite capability and larger programming margin. The phenomena of multiple snapbacks can also be observed from the simulated I-V characteristics. Relying on the simulated results by the PCM HSPICE model, the stacked PCM could be one feasible approach for accomplishing multilevel storage in PCM.