Dependence of DC parameters on layout and low-frequency noise behavior in strained-si nMOSFETs fabricated by stress-memorization technique

Yao Tsung Huang, San Lein Wu, Shoou Jinn Chang, Cheng Wen Kuo, Ya Ting Chen, Yao Chin Cheng, Osbert Cheng

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

The impact of stress-memorization technique (SMT)-induced tensile strain on the layout dependence of nMOSFET characteristics is investigated. It is found that the incorporation of the SMT process provides up to 12% improvement in transconductance and 9% enhancement in on-state current for nMOSFETs with a source/drain length (LS/D) of 1.76 μmand W = 0.5. The characteristics of the SMT device become more sensitive to the layout geometry as LS/D and W are down to 0.5 and 0.25 μm, respectively. Moreover, low-frequency measurements reveal that the interface quality of the SMT device is the same as that of the control devices. Furthermore, it is found that the mechanism of 1 noise in the SMT device can be properly interpreted by the unified model.

Original languageEnglish
Article number5439695
Pages (from-to)500-502
Number of pages3
JournalIEEE Electron Device Letters
Volume31
Issue number5
DOIs
Publication statusPublished - 2010 May

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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