Design and fabrication of 0/1-level RF-via interconnect for RF-MEMS packaging applications

Li Han Hsu; Wei Cheng Wu; Edward Yi Chang; Herbert Zirath; Yun Chi Wu; Chin Te Wang; Ching Ting Lee

doi:10.1109/TADVP.2009.2034137

Design and fabrication of 0/1-level RF-via interconnect for RF-MEMS packaging applications

Li Han Hsu, Wei Cheng Wu, Edward Yi Chang, Herbert Zirath, Yun Chi Wu, Chin Te Wang, Ching Ting Lee

Department of Photonics

Research output: Contribution to journal › Article › peer-review

7 Citations (Scopus)

Abstract

This paper presents the parametric study of RF-via (0-level) and flip-chip bump (1-level) transitions for applications of packaging coplanar RF-MEMS devices. The key parameters were found to be the bumps' and vias' positions and the overlap of the metal pads, which should be carefully considered in the entire two levels of packages. The length of the backside transmission line, determining the MEMS substrate area, showed minor influence on the interconnect performance. With the experimental results, the design rules have been developed and established. The optimized interconnect structure for the two levels of packages demonstrates the return loss beyond 15 dB and the insertion loss within 0.6 dB from dc to 60 GHz.

Original language	English
Article number	5345704
Pages (from-to)	30-36
Number of pages	7
Journal	IEEE Transactions on Advanced Packaging
Volume	33
Issue number	1
DOIs	https://doi.org/10.1109/TADVP.2009.2034137
Publication status	Published - 2010 Feb

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/TADVP.2009.2034137

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title = "Design and fabrication of 0/1-level RF-via interconnect for RF-MEMS packaging applications",

abstract = "This paper presents the parametric study of RF-via (0-level) and flip-chip bump (1-level) transitions for applications of packaging coplanar RF-MEMS devices. The key parameters were found to be the bumps' and vias' positions and the overlap of the metal pads, which should be carefully considered in the entire two levels of packages. The length of the backside transmission line, determining the MEMS substrate area, showed minor influence on the interconnect performance. With the experimental results, the design rules have been developed and established. The optimized interconnect structure for the two levels of packages demonstrates the return loss beyond 15 dB and the insertion loss within 0.6 dB from dc to 60 GHz.",

author = "Hsu, {Li Han} and Wu, {Wei Cheng} and Chang, {Edward Yi} and Herbert Zirath and Wu, {Yun Chi} and Wang, {Chin Te} and Lee, {Ching Ting}",

note = "Funding Information: Manuscript received August 13, 2008; revised February 09, 2009; July 09, 2009. First published December 04, 2009; current version published February 26, 2010. This work was supported in part by the National Science Council under Contract NSC 96-2752-E-009-001-PAE and in part the Ministry of Economic Affairs, Taiwan, under Contract 95-EC-17-A-05-S1-020. This work was recommended for publication by Associate Editor A. Chiou upon evaluation of the reviewers comments.",

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doi = "10.1109/TADVP.2009.2034137",

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AU - Wu, Yun Chi

AU - Wang, Chin Te

AU - Lee, Ching Ting

N1 - Funding Information: Manuscript received August 13, 2008; revised February 09, 2009; July 09, 2009. First published December 04, 2009; current version published February 26, 2010. This work was supported in part by the National Science Council under Contract NSC 96-2752-E-009-001-PAE and in part the Ministry of Economic Affairs, Taiwan, under Contract 95-EC-17-A-05-S1-020. This work was recommended for publication by Associate Editor A. Chiou upon evaluation of the reviewers comments.

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Design and fabrication of 0/1-level RF-via interconnect for RF-MEMS packaging applications

Abstract

All Science Journal Classification (ASJC) codes

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