Design and fabrication of 0/1-level RF-via interconnect for RF-MEMS packaging applications

Li Han Hsu, Wei Cheng Wu, Edward Yi Chang, Herbert Zirath, Yun Chi Wu, Chin Te Wang, Ching Ting Lee

Research output: Contribution to journalArticlepeer-review

7 Citations (Scopus)


This paper presents the parametric study of RF-via (0-level) and flip-chip bump (1-level) transitions for applications of packaging coplanar RF-MEMS devices. The key parameters were found to be the bumps' and vias' positions and the overlap of the metal pads, which should be carefully considered in the entire two levels of packages. The length of the backside transmission line, determining the MEMS substrate area, showed minor influence on the interconnect performance. With the experimental results, the design rules have been developed and established. The optimized interconnect structure for the two levels of packages demonstrates the return loss beyond 15 dB and the insertion loss within 0.6 dB from dc to 60 GHz.

Original languageEnglish
Article number5345704
Pages (from-to)30-36
Number of pages7
JournalIEEE Transactions on Advanced Packaging
Issue number1
Publication statusPublished - 2010 Feb

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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