Design and implementation of an efficient architecture for higher order statistics with DWT

Lih Yih Chiou; Hsieh Wei Lee; Sheau Fang Lei; Bin Da Liu

doi:10.1109/VDAT.2005.1500077

Design and implementation of an efficient architecture for higher order statistics with DWT

Lih Yih Chiou, Hsieh Wei Lee, Sheau Fang Lei, Bin Da Liu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Higher order statistical metric has the capability to extract the signal feature of non-stationary waveforms that the second order statistics can't. This paper proposes an efficient architecture for the frequency domain kurtosis metric, which is an example of the higher order statistics using DWT bit streams. The hardware design methodology emphasizes efficiency on area and time to meet the technological challenges of compactness and portability for biomedical applications.

Original language	English
Title of host publication	2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Pages	287-290
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2005.1500077
Publication status	Published - 2005 Dec 1
Event	2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) - Hsinchu, Taiwan Duration: 2005 Apr 27 → 2005 Apr 29

Publication series

Name	2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Volume	2005

Other

Other	2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Country	Taiwan
City	Hsinchu
Period	05-04-27 → 05-04-29

All Science Journal Classification (ASJC) codes

Engineering(all)

Access to Document

10.1109/VDAT.2005.1500077

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Chiou, L. Y., Lee, H. W., Lei, S. F., & Liu, B. D. (2005). Design and implementation of an efficient architecture for higher order statistics with DWT. In 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) (pp. 287-290). [1500077] (2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT); Vol. 2005). https://doi.org/10.1109/VDAT.2005.1500077

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abstract = "Higher order statistical metric has the capability to extract the signal feature of non-stationary waveforms that the second order statistics can't. This paper proposes an efficient architecture for the frequency domain kurtosis metric, which is an example of the higher order statistics using DWT bit streams. The hardware design methodology emphasizes efficiency on area and time to meet the technological challenges of compactness and portability for biomedical applications.",

author = "Chiou, {Lih Yih} and Lee, {Hsieh Wei} and Lei, {Sheau Fang} and Liu, {Bin Da}",

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booktitle = "2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)",

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Chiou, LY, Lee, HW, Lei, SF & Liu, BD 2005, Design and implementation of an efficient architecture for higher order statistics with DWT. in 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)., 1500077, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT), vol. 2005, pp. 287-290, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT), Hsinchu, Taiwan, 05-04-27. https://doi.org/10.1109/VDAT.2005.1500077

Design and implementation of an efficient architecture for higher order statistics with DWT. / Chiou, Lih Yih; Lee, Hsieh Wei; Lei, Sheau Fang; Liu, Bin Da.

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT). 2005. p. 287-290 1500077 (2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT); Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Chiou LY, Lee HW, Lei SF, Liu BD. Design and implementation of an efficient architecture for higher order statistics with DWT. In 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT). 2005. p. 287-290. 1500077. (2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)). https://doi.org/10.1109/VDAT.2005.1500077