TY - GEN
T1 - Design and implementation of efficient reed-solomon decoders for multi-mode applications
AU - Shieh, Ming Der
AU - Lu, Yung Kuei
AU - Chung, Shen Ming
AU - Chen, Jun Hong
PY - 2006
Y1 - 2006
N2 - We present a multi-mode Reed-Solomon decoder based on the reformulated inversionless Berlekamp-Massey algorithm, which can retain the throughput rate of the reformulated architecture in many practical applications. With the developed coefficient-selector-free multi-mode arrangement, the resulting design possesses not only area-efficient property but also very simple and regular interconnect topology that makes it very suitable for VLSI realization. Implementation results exhibit that the achievable throughput rate of the developed decoder for n≤255 and 0≤t≤8, implemented in UMC 0.18μm 1P6M process, is 3.2Gbps at the maximum clock rate of 400MHz and the total gate count is 22,931. Compared with the existing work based on extended Euclidean algorithm, our development provides both area and speed advantages and can be used for multi-standard applications.
AB - We present a multi-mode Reed-Solomon decoder based on the reformulated inversionless Berlekamp-Massey algorithm, which can retain the throughput rate of the reformulated architecture in many practical applications. With the developed coefficient-selector-free multi-mode arrangement, the resulting design possesses not only area-efficient property but also very simple and regular interconnect topology that makes it very suitable for VLSI realization. Implementation results exhibit that the achievable throughput rate of the developed decoder for n≤255 and 0≤t≤8, implemented in UMC 0.18μm 1P6M process, is 3.2Gbps at the maximum clock rate of 400MHz and the total gate count is 22,931. Compared with the existing work based on extended Euclidean algorithm, our development provides both area and speed advantages and can be used for multi-standard applications.
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M3 - Conference contribution
AN - SCOPUS:34547240969
SN - 0780393902
SN - 9780780393905
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 289
EP - 292
BT - ISCAS 2006
T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Y2 - 21 May 2006 through 24 May 2006
ER -