Design and implementation of window delay-line ADC for low-power DC-DC SMPS

Huei Shan Chen, Chun Hung Yang, Chien Hung Tsai, Guan Lin Li

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

A window delay-line analog-to-digital converter (ADC) with programmable resolutions for digitally-controlled switch-mode power supplies (SMPS) used in low-power portable applications is proposed in this paper. Due to its simple, low-power architecture and small silicon area, this ADC can be fully integrated with a digital controller. The proposed ADC quantizes the output converter voltage within a window of the reference voltage. The ADC has been fabricated in a TSMC 0.18μm CMOS technology and verified as a part of a 976.56 KHz, 3.6 to 1.2 V buck DC-DC converter.

Original languageEnglish
Title of host publication2012 IEEE 13th Workshop on Control and Modeling for Power Electronics, COMPEL 2012
DOIs
Publication statusPublished - 2012 Oct 1
Event2012 IEEE 13th Workshop on Control and Modeling for Power Electronics, COMPEL 2012 - Kyoto, Japan
Duration: 2012 Jul 102012 Jul 13

Publication series

Name2012 IEEE 13th Workshop on Control and Modeling for Power Electronics, COMPEL 2012

Other

Other2012 IEEE 13th Workshop on Control and Modeling for Power Electronics, COMPEL 2012
CountryJapan
CityKyoto
Period12-07-1012-07-13

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Modelling and Simulation

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    Chen, H. S., Yang, C. H., Tsai, C. H., & Li, G. L. (2012). Design and implementation of window delay-line ADC for low-power DC-DC SMPS. In 2012 IEEE 13th Workshop on Control and Modeling for Power Electronics, COMPEL 2012 [6251735] (2012 IEEE 13th Workshop on Control and Modeling for Power Electronics, COMPEL 2012). https://doi.org/10.1109/COMPEL.2012.6251735