The inherent data dependency and various types of syntax elements existing in the CABAC encoding process will result in dramatically increased complexity if two bins obtained from binarizing syntax elements are handled per clock cycle. By analyzing the distribution of binarized bins in different video sequences, we show how to efficiently improve the encoding rate with a limited increase in hardware complexity by only allowing a certain type of syntax elements to be processed two bins at a time. Together with the presented range renovation reordering and memory arrangement schemes, our design can achieve an encoding rate of up to 270 Mbps with very limited hardware overhead. Meanwhile, we also describe techniques to effectively test the manufacture faults in chip implementation. Experimental results exhibit the advantages of employing the developed design and test schemes.