Design and test of a scalable security processor

Chih Pin Su; Chen Hsing Wang; Kuo Liang Cheng; Chih Tsun Huang; Cheng Wen Wu

Design and test of a scalable security processor

Chih Pin Su, Chen Hsing Wang, Kuo Liang Cheng, Chih Tsun Huang, Cheng Wen Wu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

This paper presents a security processor to accelerate cryptographic processing in modern security applications. Our security processor is capable of popular cryptographic functions such as RSA, AES, hashing and random number generation, etc. With proposed Crypto-DMA controller, data gathering and scattering become flexible for security processing, using a simple descriptor-based programming model. The architecture of the security processor with its core-based platform is scalable and configurable for security variations in performance, cost and power consumption. Different number of data channels and crypto-engines can be used to meet the specifications. In addition, a DFT platform is also implemented for the design-test integration. The security processor has been fabricated with 0.18μm CMOS technology, The core area is 3.899mm times; 2.296mm (525K gates approximately) and the operating clock rate is 83MHz.

Original language	English
Title of host publication	Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Pages	372-375
Number of pages	4
Publication status	Published - 2005 Dec 1
Event	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China Duration: 2005 Jan 18 → 2005 Jan 21

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	1

Other

Other	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Country/Territory	China
City	Shanghai
Period	05-01-18 → 05-01-21

All Science Journal Classification (ASJC) codes

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Cite this

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title = "Design and test of a scalable security processor",

abstract = "This paper presents a security processor to accelerate cryptographic processing in modern security applications. Our security processor is capable of popular cryptographic functions such as RSA, AES, hashing and random number generation, etc. With proposed Crypto-DMA controller, data gathering and scattering become flexible for security processing, using a simple descriptor-based programming model. The architecture of the security processor with its core-based platform is scalable and configurable for security variations in performance, cost and power consumption. Different number of data channels and crypto-engines can be used to meet the specifications. In addition, a DFT platform is also implemented for the design-test integration. The security processor has been fabricated with 0.18μm CMOS technology, The core area is 3.899mm times; 2.296mm (525K gates approximately) and the operating clock rate is 83MHz.",

author = "Su, {Chih Pin} and Wang, {Chen Hsing} and Cheng, {Kuo Liang} and Huang, {Chih Tsun} and Wu, {Cheng Wen}",

year = "2005",

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day = "1",

language = "English",

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series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

pages = "372--375",

booktitle = "Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005",

note = "2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 ; Conference date: 18-01-2005 Through 21-01-2005",

}

Su, CP, Wang, CH, Cheng, KL, Huang, CT & Wu, CW 2005, Design and test of a scalable security processor. in Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005., 1466191, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 1, pp. 372-375, 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005, Shanghai, China, 05-01-18.

Design and test of a scalable security processor. / Su, Chih Pin; Wang, Chen Hsing; Cheng, Kuo Liang; Huang, Chih Tsun; Wu, Cheng Wen.

Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. 2005. p. 372-375 1466191 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - This paper presents a security processor to accelerate cryptographic processing in modern security applications. Our security processor is capable of popular cryptographic functions such as RSA, AES, hashing and random number generation, etc. With proposed Crypto-DMA controller, data gathering and scattering become flexible for security processing, using a simple descriptor-based programming model. The architecture of the security processor with its core-based platform is scalable and configurable for security variations in performance, cost and power consumption. Different number of data channels and crypto-engines can be used to meet the specifications. In addition, a DFT platform is also implemented for the design-test integration. The security processor has been fabricated with 0.18μm CMOS technology, The core area is 3.899mm times; 2.296mm (525K gates approximately) and the operating clock rate is 83MHz.

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Design and test of a scalable security processor

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All Science Journal Classification (ASJC) codes

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