TY - GEN
T1 - Design and test of a scalable security processor
AU - Su, Chih Pin
AU - Wang, Chen Hsing
AU - Cheng, Kuo Liang
AU - Huang, Chih Tsun
AU - Wu, Cheng Wen
PY - 2005/12/1
Y1 - 2005/12/1
N2 - This paper presents a security processor to accelerate cryptographic processing in modern security applications. Our security processor is capable of popular cryptographic functions such as RSA, AES, hashing and random number generation, etc. With proposed Crypto-DMA controller, data gathering and scattering become flexible for security processing, using a simple descriptor-based programming model. The architecture of the security processor with its core-based platform is scalable and configurable for security variations in performance, cost and power consumption. Different number of data channels and crypto-engines can be used to meet the specifications. In addition, a DFT platform is also implemented for the design-test integration. The security processor has been fabricated with 0.18μm CMOS technology, The core area is 3.899mm times; 2.296mm (525K gates approximately) and the operating clock rate is 83MHz.
AB - This paper presents a security processor to accelerate cryptographic processing in modern security applications. Our security processor is capable of popular cryptographic functions such as RSA, AES, hashing and random number generation, etc. With proposed Crypto-DMA controller, data gathering and scattering become flexible for security processing, using a simple descriptor-based programming model. The architecture of the security processor with its core-based platform is scalable and configurable for security variations in performance, cost and power consumption. Different number of data channels and crypto-engines can be used to meet the specifications. In addition, a DFT platform is also implemented for the design-test integration. The security processor has been fabricated with 0.18μm CMOS technology, The core area is 3.899mm times; 2.296mm (525K gates approximately) and the operating clock rate is 83MHz.
UR - http://www.scopus.com/inward/record.url?scp=51849110669&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=51849110669&partnerID=8YFLogxK
U2 - 10.1145/1120725.1120872
DO - 10.1145/1120725.1120872
M3 - Conference contribution
AN - SCOPUS:51849110669
SN - 0780387368
SN - 9780780387362
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 372
EP - 375
BT - Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Y2 - 18 January 2005 through 21 January 2005
ER -