Design and test of a scalable security processor

Chih Pin Su, Chen Hsing Wang, Kuo Liang Cheng, Chih Tsun Huang, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

This paper presents a security processor to accelerate cryptographic processing in modern security applications. Our security processor is capable of popular cryptographic functions such as RSA, AES, hashing and random number generation, etc. With proposed Crypto-DMA controller, data gathering and scattering become flexible for security processing, using a simple descriptor-based programming model. The architecture of the security processor with its core-based platform is scalable and configurable for security variations in performance, cost and power consumption. Different number of data channels and crypto-engines can be used to meet the specifications. In addition, a DFT platform is also implemented for the design-test integration. The security processor has been fabricated with 0.18μm CMOS technology, The core area is 3.899mm times; 2.296mm (525K gates approximately) and the operating clock rate is 83MHz.

Original languageEnglish
Title of host publicationProceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Pages372-375
Number of pages4
Publication statusPublished - 2005 Dec 1
Event2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China
Duration: 2005 Jan 182005 Jan 21

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume1

Other

Other2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Country/TerritoryChina
CityShanghai
Period05-01-1805-01-21

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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