TY - JOUR
T1 - Design and Test Rules for CMOS Circuits to Facilitate IDDQ Testing of Bridging Faults
AU - Lee, Kuen Jong
AU - Breuer, Melvin A.
N1 - Funding Information:
Manuscript received October 1, 1990; revised February 7. 1991. This work was supported by the Defense Advanced Research Projects Agency and monitored by the Office of Naval Research under Contract N00014-87-K-0861 and by the Federal Bureau of Investigation under Contract JFBI90092. This paper was recommended by Associate Editor S . C. Seth. K.-J. Lee was with the Department of Electrical Engineering-Systems, University of Southern California, Los Angeles. He is now with the Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C. M. A. Breuer is with the Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA 90089-2560. IEEE Log Number 9105725.
PY - 1992/5
Y1 - 1992/5
N2 - IDDQ testing, or current supply monitoring (CSM), is an efficient and effective method for detecting CMOS bridging faults (BF’s). The applicability of this technique, hoever, requires careful examination. In this paper all possible BF’s between any two circuit nodes are considered, where a circuit node may be the drain, source, or gate terminal of a transistor. We first give several examples to show that under certain circumstances CSM cannot give correct test results. A circuit partitioning model is then described and a minimal set of design and test rules is presented. This set of rules is minimal in the sense that if any one of these rules is removed, then circuits exist for which CSM cannot give correct test results. When all these rules are satisfied it can be formally shown that 1) all single irredundant BF’s can be detected by single vector tests and 2) a test vector that detects a single bridging fault fxalso detects all multiple BF’s that contain f1. To enhance the applicability of CSM, test and/or design strategies for dealing with circuits that do not satisfy each rule are proposed. Such circuits include a special exclusive or gate, BiCMOS circuits, domino logic, synchronous sequential circuits, and circuits implemented by the silicon on insulator (SOI) technology.
AB - IDDQ testing, or current supply monitoring (CSM), is an efficient and effective method for detecting CMOS bridging faults (BF’s). The applicability of this technique, hoever, requires careful examination. In this paper all possible BF’s between any two circuit nodes are considered, where a circuit node may be the drain, source, or gate terminal of a transistor. We first give several examples to show that under certain circumstances CSM cannot give correct test results. A circuit partitioning model is then described and a minimal set of design and test rules is presented. This set of rules is minimal in the sense that if any one of these rules is removed, then circuits exist for which CSM cannot give correct test results. When all these rules are satisfied it can be formally shown that 1) all single irredundant BF’s can be detected by single vector tests and 2) a test vector that detects a single bridging fault fxalso detects all multiple BF’s that contain f1. To enhance the applicability of CSM, test and/or design strategies for dealing with circuits that do not satisfy each rule are proposed. Such circuits include a special exclusive or gate, BiCMOS circuits, domino logic, synchronous sequential circuits, and circuits implemented by the silicon on insulator (SOI) technology.
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U2 - 10.1109/43.127626
DO - 10.1109/43.127626
M3 - Article
AN - SCOPUS:0026869827
SN - 0278-0070
VL - 11
SP - 659
EP - 670
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 5
ER -