Design consideration of emitter-base junction structure for InGaP/GaAs heterojunction bipolar transistors

Shiou Ying Cheng, Wen Lung Chang, Hsi Jen Pan, Yung Hsin Shie, Wen-Chau Liu

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

In this paper, the different designs of emitter-base junction including the employment of the δ-doping sheet and setback layer are presented and studied. A theoretical model is used to analyze the performances of the proposed different InGaP/GaAs heterojunction bipolar transistors (HBTs). Experimentally, a new InGaP/GaAs HBT with a δ-doping sheet and a setback layer inserting between emitter-base heterointerface is fabricated successfully. From the theoretical analysis and experimental results, it is found that the insertion of the δ-doping sheet and the setback layer can effectively eliminate the undesired potential spike at N-InGaP/p+ -GaAs heterointerface. The experimental common-emitter current gain of 280 at collector current of 85 mA and a low offset voltage of 55 mV are achieved. In addition, a current gain of 11 at very small collector current of 0.5 μm without passivation is obtained.

Original languageEnglish
Pages (from-to)297-304
Number of pages8
JournalSolid-State Electronics
Volume43
Issue number2
DOIs
Publication statusPublished - 1999 Jan 1

Fingerprint

Heterojunction bipolar transistors
bipolar transistors
heterojunctions
emitters
Doping (additives)
accumulators
spike potentials
Passivation
low voltage
passivity
insertion
Electric potential
gallium arsenide

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

Cite this

Cheng, Shiou Ying ; Chang, Wen Lung ; Pan, Hsi Jen ; Shie, Yung Hsin ; Liu, Wen-Chau. / Design consideration of emitter-base junction structure for InGaP/GaAs heterojunction bipolar transistors. In: Solid-State Electronics. 1999 ; Vol. 43, No. 2. pp. 297-304.
@article{04be55293a1e4e0490bc9d4ba2e0f0f9,
title = "Design consideration of emitter-base junction structure for InGaP/GaAs heterojunction bipolar transistors",
abstract = "In this paper, the different designs of emitter-base junction including the employment of the δ-doping sheet and setback layer are presented and studied. A theoretical model is used to analyze the performances of the proposed different InGaP/GaAs heterojunction bipolar transistors (HBTs). Experimentally, a new InGaP/GaAs HBT with a δ-doping sheet and a setback layer inserting between emitter-base heterointerface is fabricated successfully. From the theoretical analysis and experimental results, it is found that the insertion of the δ-doping sheet and the setback layer can effectively eliminate the undesired potential spike at N-InGaP/p+ -GaAs heterointerface. The experimental common-emitter current gain of 280 at collector current of 85 mA and a low offset voltage of 55 mV are achieved. In addition, a current gain of 11 at very small collector current of 0.5 μm without passivation is obtained.",
author = "Cheng, {Shiou Ying} and Chang, {Wen Lung} and Pan, {Hsi Jen} and Shie, {Yung Hsin} and Wen-Chau Liu",
year = "1999",
month = "1",
day = "1",
doi = "10.1016/S0038-1101(98)00268-8",
language = "English",
volume = "43",
pages = "297--304",
journal = "Solid-State Electronics",
issn = "0038-1101",
publisher = "Elsevier Limited",
number = "2",

}

Design consideration of emitter-base junction structure for InGaP/GaAs heterojunction bipolar transistors. / Cheng, Shiou Ying; Chang, Wen Lung; Pan, Hsi Jen; Shie, Yung Hsin; Liu, Wen-Chau.

In: Solid-State Electronics, Vol. 43, No. 2, 01.01.1999, p. 297-304.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Design consideration of emitter-base junction structure for InGaP/GaAs heterojunction bipolar transistors

AU - Cheng, Shiou Ying

AU - Chang, Wen Lung

AU - Pan, Hsi Jen

AU - Shie, Yung Hsin

AU - Liu, Wen-Chau

PY - 1999/1/1

Y1 - 1999/1/1

N2 - In this paper, the different designs of emitter-base junction including the employment of the δ-doping sheet and setback layer are presented and studied. A theoretical model is used to analyze the performances of the proposed different InGaP/GaAs heterojunction bipolar transistors (HBTs). Experimentally, a new InGaP/GaAs HBT with a δ-doping sheet and a setback layer inserting between emitter-base heterointerface is fabricated successfully. From the theoretical analysis and experimental results, it is found that the insertion of the δ-doping sheet and the setback layer can effectively eliminate the undesired potential spike at N-InGaP/p+ -GaAs heterointerface. The experimental common-emitter current gain of 280 at collector current of 85 mA and a low offset voltage of 55 mV are achieved. In addition, a current gain of 11 at very small collector current of 0.5 μm without passivation is obtained.

AB - In this paper, the different designs of emitter-base junction including the employment of the δ-doping sheet and setback layer are presented and studied. A theoretical model is used to analyze the performances of the proposed different InGaP/GaAs heterojunction bipolar transistors (HBTs). Experimentally, a new InGaP/GaAs HBT with a δ-doping sheet and a setback layer inserting between emitter-base heterointerface is fabricated successfully. From the theoretical analysis and experimental results, it is found that the insertion of the δ-doping sheet and the setback layer can effectively eliminate the undesired potential spike at N-InGaP/p+ -GaAs heterointerface. The experimental common-emitter current gain of 280 at collector current of 85 mA and a low offset voltage of 55 mV are achieved. In addition, a current gain of 11 at very small collector current of 0.5 μm without passivation is obtained.

UR - http://www.scopus.com/inward/record.url?scp=0033079747&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033079747&partnerID=8YFLogxK

U2 - 10.1016/S0038-1101(98)00268-8

DO - 10.1016/S0038-1101(98)00268-8

M3 - Article

AN - SCOPUS:0033079747

VL - 43

SP - 297

EP - 304

JO - Solid-State Electronics

JF - Solid-State Electronics

SN - 0038-1101

IS - 2

ER -