Design-for-test circuit for the reduced code based linearity test method in pipelined ADCs with digital error correction technique

Jin Fu Lin, Soon Jyh Chang, Chih Hao Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

In our previous work, the reduced code based method has been proposed to significantly reduce the linearity test time of a pipelined ADC [1]. The digital error correction (DEC) technique is extensively employed in a pipelined ADC. A pipelined ADC with this technique can tolerate large comparator offset without degrading the ADC linearity. However, in this paper, we find that comparator offsets would cause large linearity test error when the reduced code based method is applied to a pipelined ADC with the DEC technique. In order to overcome this problem, a simple digital Design-For-Test (DfT) circuit is proposed. Simulation results demonstrate the effectiveness of the refined reduced code based method combined with the proposed DfT circuit.

Original languageEnglish
Title of host publicationProceedings of the 18th Asian Test Symposium, ATS 2009
Pages57-62
Number of pages6
DOIs
Publication statusPublished - 2009 Dec 1
Event18th Asian Test Symposium, ATS 2009 - Taichung, Taiwan
Duration: 2009 Nov 232009 Nov 26

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Other

Other18th Asian Test Symposium, ATS 2009
CountryTaiwan
CityTaichung
Period09-11-2309-11-26

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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