Design-for-test circuit for the reduced code based linearity test method in pipelined ADCs with digital error correction technique

Jin Fu Lin; Soon Jyh Chang; Chih Hao Huang

doi:10.1109/ATS.2009.18

Design-for-test circuit for the reduced code based linearity test method in pipelined ADCs with digital error correction technique

Jin Fu Lin, Soon Jyh Chang, Chih Hao Huang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

In our previous work, the reduced code based method has been proposed to significantly reduce the linearity test time of a pipelined ADC [1]. The digital error correction (DEC) technique is extensively employed in a pipelined ADC. A pipelined ADC with this technique can tolerate large comparator offset without degrading the ADC linearity. However, in this paper, we find that comparator offsets would cause large linearity test error when the reduced code based method is applied to a pipelined ADC with the DEC technique. In order to overcome this problem, a simple digital Design-For-Test (DfT) circuit is proposed. Simulation results demonstrate the effectiveness of the refined reduced code based method combined with the proposed DfT circuit.

Original language	English
Title of host publication	Proceedings of the 18th Asian Test Symposium, ATS 2009
Pages	57-62
Number of pages	6
DOIs	https://doi.org/10.1109/ATS.2009.18
Publication status	Published - 2009 Dec 1
Event	18th Asian Test Symposium, ATS 2009 - Taichung, Taiwan Duration: 2009 Nov 23 → 2009 Nov 26

Publication series

Name	Proceedings of the Asian Test Symposium
ISSN (Print)	1081-7735

Other

Other	18th Asian Test Symposium, ATS 2009
Country/Territory	Taiwan
City	Taichung
Period	09-11-23 → 09-11-26

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ATS.2009.18

Cite this

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title = "Design-for-test circuit for the reduced code based linearity test method in pipelined ADCs with digital error correction technique",

abstract = "In our previous work, the reduced code based method has been proposed to significantly reduce the linearity test time of a pipelined ADC [1]. The digital error correction (DEC) technique is extensively employed in a pipelined ADC. A pipelined ADC with this technique can tolerate large comparator offset without degrading the ADC linearity. However, in this paper, we find that comparator offsets would cause large linearity test error when the reduced code based method is applied to a pipelined ADC with the DEC technique. In order to overcome this problem, a simple digital Design-For-Test (DfT) circuit is proposed. Simulation results demonstrate the effectiveness of the refined reduced code based method combined with the proposed DfT circuit.",

author = "Lin, {Jin Fu} and Chang, {Soon Jyh} and Huang, {Chih Hao}",

year = "2009",

month = dec,

day = "1",

doi = "10.1109/ATS.2009.18",

language = "English",

isbn = "9780769538648",

series = "Proceedings of the Asian Test Symposium",

pages = "57--62",

booktitle = "Proceedings of the 18th Asian Test Symposium, ATS 2009",

note = "18th Asian Test Symposium, ATS 2009 ; Conference date: 23-11-2009 Through 26-11-2009",

}

Lin, JF, Chang, SJ & Huang, CH 2009, Design-for-test circuit for the reduced code based linearity test method in pipelined ADCs with digital error correction technique. in Proceedings of the 18th Asian Test Symposium, ATS 2009., 5359410, Proceedings of the Asian Test Symposium, pp. 57-62, 18th Asian Test Symposium, ATS 2009, Taichung, Taiwan, 09-11-23. https://doi.org/10.1109/ATS.2009.18

Design-for-test circuit for the reduced code based linearity test method in pipelined ADCs with digital error correction technique. / Lin, Jin Fu; Chang, Soon Jyh; Huang, Chih Hao.
Proceedings of the 18th Asian Test Symposium, ATS 2009. 2009. p. 57-62 5359410 (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - Design-for-test circuit for the reduced code based linearity test method in pipelined ADCs with digital error correction technique

AU - Lin, Jin Fu

AU - Chang, Soon Jyh

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N2 - In our previous work, the reduced code based method has been proposed to significantly reduce the linearity test time of a pipelined ADC [1]. The digital error correction (DEC) technique is extensively employed in a pipelined ADC. A pipelined ADC with this technique can tolerate large comparator offset without degrading the ADC linearity. However, in this paper, we find that comparator offsets would cause large linearity test error when the reduced code based method is applied to a pipelined ADC with the DEC technique. In order to overcome this problem, a simple digital Design-For-Test (DfT) circuit is proposed. Simulation results demonstrate the effectiveness of the refined reduced code based method combined with the proposed DfT circuit.

AB - In our previous work, the reduced code based method has been proposed to significantly reduce the linearity test time of a pipelined ADC [1]. The digital error correction (DEC) technique is extensively employed in a pipelined ADC. A pipelined ADC with this technique can tolerate large comparator offset without degrading the ADC linearity. However, in this paper, we find that comparator offsets would cause large linearity test error when the reduced code based method is applied to a pipelined ADC with the DEC technique. In order to overcome this problem, a simple digital Design-For-Test (DfT) circuit is proposed. Simulation results demonstrate the effectiveness of the refined reduced code based method combined with the proposed DfT circuit.

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Design-for-test circuit for the reduced code based linearity test method in pipelined ADCs with digital error correction technique

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