Abstract
Static (DC) and dynamic (AC) hot carrier degradation mechanisms were reviewed. Circuit performance degradation has been correlated to individual NMOS or PMOS device under DC stress. AC degradation model calibration and evaluation guidelines were also reviewed to ensure the use of hot-carrier reliability simulation tools in circuit level. As an example, thousand-hour inverter ring oscillator speed degradation data with different fanout, stress voltages, channel length, and processes are compared with that obtained from reliability simulation. The results show that reliability simulation is a powerful tool for logic circuit design optimization. It can predict the long-term circuit hot-carrier degradation accurately. The reliability of inverter, NAND, and NOR structures are also simulated and compared.
| Original language | English |
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| Pages (from-to) | 525-531 |
| Number of pages | 7 |
| Journal | Proceedings of the Custom Integrated Circuits Conference |
| Publication status | Published - 1998 |
| Event | Proceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA Duration: 1998 May 11 → 1998 May 14 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering