Design issues and insights of multi-fin bulk silicon FinFETs

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Multi-fin bulk silicon FinFET-based design issues and implications using 3D numerical simulation are presented for the first time. In order to gain sufficient drive current of each transistor, multi-fin layout is inevitable due to limited aspect ratio or fin height. However, how the multi-fin design impacts the circuit performance needs to be taken into account. Because of non-planar nature of the fin, conventional concept of multi-finger design in bulk CMOS technology does not apply. We found an extra leakage path underneath the fin spacing between source and drain. Such impact can be mitigated by additional substrate doping and proper gate-to-substrate isolation. Based on the proposed design window at a tight pitch control, good performance can be achieved while meeting leakage current requirement.

Original languageEnglish
Title of host publicationProceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012
Pages723-726
Number of pages4
DOIs
Publication statusPublished - 2012 Jul 16
Event13th International Symposium on Quality Electronic Design, ISQED 2012 - Santa Clara, CA, United States
Duration: 2012 Mar 192012 Mar 21

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other13th International Symposium on Quality Electronic Design, ISQED 2012
CountryUnited States
CitySanta Clara, CA
Period12-03-1912-03-21

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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