Design of 60-GHz 90-nm CMOS balanced power amplifier with miniaturized quadrature hybrids

Chien Chih Lin, Chun Han Yu, Hsin Chih Kuo, Huey-Ru Chuang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

This paper presents a 60-GHz CMOS balanced power amplifier (PA) with miniaturized quadrature hybrids using 90-nm CMOS technology. To improve the output power and provide an area-efficient solution for the balanced PA design, a compact 3-dB quadrature hybrid constructed by a broadside-coupled scheme is employed as a low-insertion-loss power splitter/combiner. With a very short effective guided wavelength of 0.072 λg, the simulated insertion loss and phase difference of the quadrature hybrids are better than 0.5 dB and 90° ± 0.2°, respectively. The designed PA reaches a power gain exceeding 13.2 dB and a saturation power of 10.7 dBm with a power-added efficiency (PAE) more than 9 % at 60 GHz. The power consumption of the PA is 109 mW at a 1.2 V supply voltage. The chip size is 0.68 mm 2.

Original languageEnglish
Title of host publicationPAWR 2014 - Proceedings
Subtitle of host publication2014 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications
PublisherIEEE Computer Society
Pages52-54
Number of pages3
ISBN (Print)9781479927784
DOIs
Publication statusPublished - 2014 Jan 1
Event2014 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications, PAWR 2014 - Newport Beach, CA, United States
Duration: 2014 Jan 192014 Jan 22

Publication series

NamePAWR 2014 - Proceedings: 2014 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications

Other

Other2014 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications, PAWR 2014
Country/TerritoryUnited States
CityNewport Beach, CA
Period14-01-1914-01-22

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications

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