Design of 60-GHz compact and low-insertion loss stepped-impedance coupled-line CMOS on-chip bandpass filter

Po Kai Chuang, Lung Kai Yeh, Huey Ru Chuang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents the design and implementation of a 60-GHz compact and low-insertion loss on-chip bandpass filter (BPF) with using a 0.18-μm standard CMOS process. For size reduction, the symmetric short-ended parallel coupled line with cascaded transmission lines is loaded with open-ended two-section stepped-impedance (SI) transmission lines. The final layout structure can be further miniaturized by properly folding the resonators. The measured results show that the fabricated BPF exhibits an insertion loss less than 3 dB and a return loss better than 16 dB. Considering the trade-off between the insertion loss and the band-edge cutoff rate, the transmission zero designed by the SI transmission lines is located at 80 GHz. The chip core size is 0.23 × 0.31 mm2 (0.09 × 0.12 λg2).

Original languageEnglish
Title of host publication2014 Asia-Pacific Microwave Conference Proceedings, APMC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1232-1234
Number of pages3
ISBN (Electronic)9784902339314
Publication statusPublished - 2014 Mar 25
Event2014 Asia-Pacific Microwave Conference, APMC 2014 - Sendai, Japan
Duration: 2014 Nov 42014 Nov 7

Publication series

Name2014 Asia-Pacific Microwave Conference Proceedings, APMC 2014

Other

Other2014 Asia-Pacific Microwave Conference, APMC 2014
CountryJapan
CitySendai
Period14-11-0414-11-07

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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