Design of 60-GHz compact and low-insertion loss stepped-impedance coupled-line CMOS on-chip bandpass filter

This paper presents the design and implementation of a 60-GHz compact and low-insertion loss on-chip bandpass filter (BPF) with using a 0.18-μm standard CMOS process. For size reduction, the symmetric short-ended parallel coupled line with cascaded transmission lines is loaded with open-ended two-section stepped-impedance (SI) transmission lines. The final layout structure can be further miniaturized by properly folding the resonators. The measured results show that the fabricated BPF exhibits an insertion loss less than 3 dB and a return loss better than 16 dB. Considering the trade-off between the insertion loss and the band-edge cutoff rate, the transmission zero designed by the SI transmission lines is located at 80 GHz. The chip core size is 0.23 × 0.31 mm² (0.09 × 0.12 λ_g²).