Design of 60-GHz CPW-fed CMOS On-chip integrated antenna-filter

Kai Hsiang Tsai, Lung Kai Yeh, Pei Chun Kuo, Huey-Ru Chuang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

This paper presents a 60-GHz millimeter- wave on-chip integrated Yagi-antenna-filter fabricated with a 0.18-μm CMOS process. An FEM-based 3-D full-wave EM solver, HFSS, is used for design simulation. The measured input VSWR of the fabricated on-chip Yagi-antenna-filter is less than 2 from 55 to 65 GHz. The measured maximum power gain is about -14 dBi. The front-to-back ratio of the radiation pattern is about 14 dB.

Original languageEnglish
Title of host publicationEuCAP 2010 - The 4th European Conference on Antennas and Propagation
Publication statusPublished - 2010 Aug 12
Event4th European Conference on Antennas and Propagation, EuCAP 2010 - Barcelona, Spain
Duration: 2010 Apr 122010 Apr 16

Publication series

NameEuCAP 2010 - The 4th European Conference on Antennas and Propagation

Other

Other4th European Conference on Antennas and Propagation, EuCAP 2010
CountrySpain
CityBarcelona
Period10-04-1210-04-16

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Design of 60-GHz CPW-fed CMOS On-chip integrated antenna-filter'. Together they form a unique fingerprint.

  • Cite this

    Tsai, K. H., Yeh, L. K., Kuo, P. C., & Chuang, H-R. (2010). Design of 60-GHz CPW-fed CMOS On-chip integrated antenna-filter. In EuCAP 2010 - The 4th European Conference on Antennas and Propagation [5505848] (EuCAP 2010 - The 4th European Conference on Antennas and Propagation).