Design of a 60-GHz down-converting dual-gate mixer in 130-nm CMOS technology

Hsin Chih Kuo; Chu Yun Yang; Jin Fu Yeh; Huey Ru Chuang; Tzuen Hsi Huang

doi:10.1109/EUMC.2009.5296523

Design of a 60-GHz down-converting dual-gate mixer in 130-nm CMOS technology

Hsin Chih Kuo, Chu Yun Yang, Jin Fu Yeh, Huey Ru Chuang, Tzuen Hsi Huang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

A 60-GHz down-converting dual-gate mixer, fabricated in the 0.13-μm CMOS process, for WPAN applications is presented. The mixer utilizes the dual-gate topology and adds a buffer to avoid loading effects. A good agreement between simulation and measurements is observed. The mixer exhibits a conversion loss of 2.7 dB, input 1-dB compression point of -8 dBm at RF of 60 GHz, IF of 5 GHz and LO power of 0 dBm. The total power consumption is 16.8 mW, 7.2 mW for the core mixer and 9.6 mW for the buffer.

Original language	English
Title of host publication	European Microwave Week 2009, EuMW 2009
Subtitle of host publication	Science, Progress and Quality at Radiofrequencies, Conference Proceedings - 39th European Microwave Conference, EuMC 2009
Pages	405-408
Number of pages	4
DOIs	https://doi.org/10.1109/EUMC.2009.5296523
Publication status	Published - 2009 Dec 1
Event	European Microwave Week 2009, EuMW 2009: Science, Progress and Quality at Radiofrequencies - 39th European Microwave Conference, EuMC 2009 - Rome, Italy Duration: 2009 Sep 28 → 2009 Oct 2

Publication series

Name	European Microwave Week 2009, EuMW 2009: Science, Progress and Quality at Radiofrequencies, Conference Proceedings - 39th European Microwave Conference, EuMC 2009

Other

Other	European Microwave Week 2009, EuMW 2009: Science, Progress and Quality at Radiofrequencies - 39th European Microwave Conference, EuMC 2009
Country/Territory	Italy
City	Rome
Period	09-09-28 → 09-10-02

All Science Journal Classification (ASJC) codes

Computer Networks and Communications
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/EUMC.2009.5296523

Cite this

Kuo, H. C., Yang, C. Y., Yeh, J. F., Chuang, H. R., & Huang, T. H. (2009). Design of a 60-GHz down-converting dual-gate mixer in 130-nm CMOS technology. In European Microwave Week 2009, EuMW 2009: Science, Progress and Quality at Radiofrequencies, Conference Proceedings - 39th European Microwave Conference, EuMC 2009 (pp. 405-408). [5296523] (European Microwave Week 2009, EuMW 2009: Science, Progress and Quality at Radiofrequencies, Conference Proceedings - 39th European Microwave Conference, EuMC 2009). https://doi.org/10.1109/EUMC.2009.5296523

Kuo, Hsin Chih ; Yang, Chu Yun ; Yeh, Jin Fu et al. / Design of a 60-GHz down-converting dual-gate mixer in 130-nm CMOS technology. European Microwave Week 2009, EuMW 2009: Science, Progress and Quality at Radiofrequencies, Conference Proceedings - 39th European Microwave Conference, EuMC 2009. 2009. pp. 405-408 (European Microwave Week 2009, EuMW 2009: Science, Progress and Quality at Radiofrequencies, Conference Proceedings - 39th European Microwave Conference, EuMC 2009).

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title = "Design of a 60-GHz down-converting dual-gate mixer in 130-nm CMOS technology",

abstract = "A 60-GHz down-converting dual-gate mixer, fabricated in the 0.13-μm CMOS process, for WPAN applications is presented. The mixer utilizes the dual-gate topology and adds a buffer to avoid loading effects. A good agreement between simulation and measurements is observed. The mixer exhibits a conversion loss of 2.7 dB, input 1-dB compression point of -8 dBm at RF of 60 GHz, IF of 5 GHz and LO power of 0 dBm. The total power consumption is 16.8 mW, 7.2 mW for the core mixer and 9.6 mW for the buffer.",

author = "Kuo, {Hsin Chih} and Yang, {Chu Yun} and Yeh, {Jin Fu} and Chuang, {Huey Ru} and Huang, {Tzuen Hsi}",

year = "2009",

month = dec,

day = "1",

doi = "10.1109/EUMC.2009.5296523",

language = "English",

isbn = "9782874870118",

series = "European Microwave Week 2009, EuMW 2009: Science, Progress and Quality at Radiofrequencies, Conference Proceedings - 39th European Microwave Conference, EuMC 2009",

pages = "405--408",

booktitle = "European Microwave Week 2009, EuMW 2009",

note = "European Microwave Week 2009, EuMW 2009: Science, Progress and Quality at Radiofrequencies - 39th European Microwave Conference, EuMC 2009 ; Conference date: 28-09-2009 Through 02-10-2009",

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Kuo, HC, Yang, CY, Yeh, JF, Chuang, HR & Huang, TH 2009, Design of a 60-GHz down-converting dual-gate mixer in 130-nm CMOS technology. in European Microwave Week 2009, EuMW 2009: Science, Progress and Quality at Radiofrequencies, Conference Proceedings - 39th European Microwave Conference, EuMC 2009., 5296523, European Microwave Week 2009, EuMW 2009: Science, Progress and Quality at Radiofrequencies, Conference Proceedings - 39th European Microwave Conference, EuMC 2009, pp. 405-408, European Microwave Week 2009, EuMW 2009: Science, Progress and Quality at Radiofrequencies - 39th European Microwave Conference, EuMC 2009, Rome, Italy, 09-09-28. https://doi.org/10.1109/EUMC.2009.5296523

Design of a 60-GHz down-converting dual-gate mixer in 130-nm CMOS technology. / Kuo, Hsin Chih; Yang, Chu Yun; Yeh, Jin Fu et al.

European Microwave Week 2009, EuMW 2009: Science, Progress and Quality at Radiofrequencies, Conference Proceedings - 39th European Microwave Conference, EuMC 2009. 2009. p. 405-408 5296523 (European Microwave Week 2009, EuMW 2009: Science, Progress and Quality at Radiofrequencies, Conference Proceedings - 39th European Microwave Conference, EuMC 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - A 60-GHz down-converting dual-gate mixer, fabricated in the 0.13-μm CMOS process, for WPAN applications is presented. The mixer utilizes the dual-gate topology and adds a buffer to avoid loading effects. A good agreement between simulation and measurements is observed. The mixer exhibits a conversion loss of 2.7 dB, input 1-dB compression point of -8 dBm at RF of 60 GHz, IF of 5 GHz and LO power of 0 dBm. The total power consumption is 16.8 mW, 7.2 mW for the core mixer and 9.6 mW for the buffer.

AB - A 60-GHz down-converting dual-gate mixer, fabricated in the 0.13-μm CMOS process, for WPAN applications is presented. The mixer utilizes the dual-gate topology and adds a buffer to avoid loading effects. A good agreement between simulation and measurements is observed. The mixer exhibits a conversion loss of 2.7 dB, input 1-dB compression point of -8 dBm at RF of 60 GHz, IF of 5 GHz and LO power of 0 dBm. The total power consumption is 16.8 mW, 7.2 mW for the core mixer and 9.6 mW for the buffer.

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Kuo HC, Yang CY, Yeh JF, Chuang HR, Huang TH. Design of a 60-GHz down-converting dual-gate mixer in 130-nm CMOS technology. In European Microwave Week 2009, EuMW 2009: Science, Progress and Quality at Radiofrequencies, Conference Proceedings - 39th European Microwave Conference, EuMC 2009. 2009. p. 405-408. 5296523. (European Microwave Week 2009, EuMW 2009: Science, Progress and Quality at Radiofrequencies, Conference Proceedings - 39th European Microwave Conference, EuMC 2009). https://doi.org/10.1109/EUMC.2009.5296523

Design of a 60-GHz down-converting dual-gate mixer in 130-nm CMOS technology

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