Design of a color reproduction neural network chip with on-chip learning capability

Jar Shone Ker; Yau-Hwang Kuo; Bin-Da Liu

Design of a color reproduction neural network chip with on-chip learning capability

Jar Shone Ker, Yau-Hwang Kuo, Bin-Da Liu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The process of eliminating color errors from the gamut mismatch, resolution conversion, quantization and non-linearity between scanner and printer is an essential issue of color reproduction. To efficiently calibrate the non-linear color distortion characteristic between color scanner and printer and to enhance the reproduction quality of color document, we develop a hardware processing module, which realizes the operation of higher-order CMAC neural network model with linear systolic array architecture, to on-line calibrate the color during the reproducing session. This mapping scheme exhibits fast computation speed in evaluating the output responses of higher-order CMAC model.

Original language	English
Title of host publication	IEEE International Conference on Image Processing
Editors	Anon
Publisher	IEEE
Pages	1023-1026
Number of pages	4
Volume	2
Publication status	Published - 1996
Event	Proceedings of the 1996 IEEE International Conference on Image Processing, ICIP'96. Part 2 (of 3) - Lausanne, Switz Duration: 1996 Sep 16 → 1996 Sep 19

Other

Other	Proceedings of the 1996 IEEE International Conference on Image Processing, ICIP'96. Part 2 (of 3)
City	Lausanne, Switz
Period	96-09-16 → 96-09-19

All Science Journal Classification (ASJC) codes

Computer Vision and Pattern Recognition
Hardware and Architecture
Electrical and Electronic Engineering

Cite this

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title = "Design of a color reproduction neural network chip with on-chip learning capability",

abstract = "The process of eliminating color errors from the gamut mismatch, resolution conversion, quantization and non-linearity between scanner and printer is an essential issue of color reproduction. To efficiently calibrate the non-linear color distortion characteristic between color scanner and printer and to enhance the reproduction quality of color document, we develop a hardware processing module, which realizes the operation of higher-order CMAC neural network model with linear systolic array architecture, to on-line calibrate the color during the reproducing session. This mapping scheme exhibits fast computation speed in evaluating the output responses of higher-order CMAC model.",

author = "Ker, {Jar Shone} and Yau-Hwang Kuo and Bin-Da Liu",

year = "1996",

language = "English",

volume = "2",

pages = "1023--1026",

editor = "Anon",

booktitle = "IEEE International Conference on Image Processing",

publisher = "IEEE",

note = "Proceedings of the 1996 IEEE International Conference on Image Processing, ICIP'96. Part 2 (of 3) ; Conference date: 16-09-1996 Through 19-09-1996",

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AU - Kuo, Yau-Hwang

AU - Liu, Bin-Da

PY - 1996

Y1 - 1996

N2 - The process of eliminating color errors from the gamut mismatch, resolution conversion, quantization and non-linearity between scanner and printer is an essential issue of color reproduction. To efficiently calibrate the non-linear color distortion characteristic between color scanner and printer and to enhance the reproduction quality of color document, we develop a hardware processing module, which realizes the operation of higher-order CMAC neural network model with linear systolic array architecture, to on-line calibrate the color during the reproducing session. This mapping scheme exhibits fast computation speed in evaluating the output responses of higher-order CMAC model.

AB - The process of eliminating color errors from the gamut mismatch, resolution conversion, quantization and non-linearity between scanner and printer is an essential issue of color reproduction. To efficiently calibrate the non-linear color distortion characteristic between color scanner and printer and to enhance the reproduction quality of color document, we develop a hardware processing module, which realizes the operation of higher-order CMAC neural network model with linear systolic array architecture, to on-line calibrate the color during the reproducing session. This mapping scheme exhibits fast computation speed in evaluating the output responses of higher-order CMAC model.

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M3 - Conference contribution

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VL - 2

SP - 1023

EP - 1026

BT - IEEE International Conference on Image Processing

A2 - Anon, null

PB - IEEE

T2 - Proceedings of the 1996 IEEE International Conference on Image Processing, ICIP'96. Part 2 (of 3)

Y2 - 16 September 1996 through 19 September 1996

ER -

Design of a color reproduction neural network chip with on-chip learning capability

Abstract

Other

All Science Journal Classification (ASJC) codes

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