Design of a pipelined and expandable sorting architecture with simple control scheme

Chi Sheng Lin, Bin-Da Liu

Research output: Contribution to journalConference article

11 Citations (Scopus)

Abstract

This paper presents a novel circuit for the pipelined and expandable sorting architecture that processes thirty-two 16-bit patterns at a time. This design is based on a compare-swap cell which can easily be cascaded to improve our sorting performance. The sorting architecture combines suitable algorithm to sort arbitrary N data patterns. The proposed hardware architecture features layout regularity and interconnection compactness, thus it can be exploited to obtain a small and efficient hardware implementation. The whole design was fabricated by TSMC 0.35μm SPQM CMOS process. The estimation results indicate that the sorter can work up to 66MHz with the power consumption less than 20mW under 3.3V supply voltage. This design is suitable for VLSI implementation. It can also be applied well when being embedded in digital signal processors.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
Publication statusPublished - 2002 Jan 1
Event2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States
Duration: 2002 May 262002 May 29

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Sorting
Hardware
Digital signal processors
Electric power utilization
Networks (circuits)
Electric potential

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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abstract = "This paper presents a novel circuit for the pipelined and expandable sorting architecture that processes thirty-two 16-bit patterns at a time. This design is based on a compare-swap cell which can easily be cascaded to improve our sorting performance. The sorting architecture combines suitable algorithm to sort arbitrary N data patterns. The proposed hardware architecture features layout regularity and interconnection compactness, thus it can be exploited to obtain a small and efficient hardware implementation. The whole design was fabricated by TSMC 0.35μm SPQM CMOS process. The estimation results indicate that the sorter can work up to 66MHz with the power consumption less than 20mW under 3.3V supply voltage. This design is suitable for VLSI implementation. It can also be applied well when being embedded in digital signal processors.",
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Design of a pipelined and expandable sorting architecture with simple control scheme. / Lin, Chi Sheng; Liu, Bin-Da.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 4, 01.01.2002.

Research output: Contribution to journalConference article

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AB - This paper presents a novel circuit for the pipelined and expandable sorting architecture that processes thirty-two 16-bit patterns at a time. This design is based on a compare-swap cell which can easily be cascaded to improve our sorting performance. The sorting architecture combines suitable algorithm to sort arbitrary N data patterns. The proposed hardware architecture features layout regularity and interconnection compactness, thus it can be exploited to obtain a small and efficient hardware implementation. The whole design was fabricated by TSMC 0.35μm SPQM CMOS process. The estimation results indicate that the sorter can work up to 66MHz with the power consumption less than 20mW under 3.3V supply voltage. This design is suitable for VLSI implementation. It can also be applied well when being embedded in digital signal processors.

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