Design of a scalable RSA and ECC crypto-processor

Ming Cheng Sun, Chih Pin Su, Chih Tsun Huang, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

In this paper, we propose a scalable word-based crypto-processor that performs modular multiplication based on the modified Montgomery algorithm for finite fields GF(P) and GF(2m). The unified crypto-processor supports scalable keys of length up to 2048 bits for RSA and 512 bits for elliptic curve cryptography (ECC). Further extension of the key length can be done easily by enlarging the memory module or using the external memory resource. With the proposed parity prediction technique, our pipelined crypto-processor achieves a 512-bit RSA encryption rate of 276 kbps and a 160-bit ECC encryption rate of 73.3 kbps for a 220 MHz clock rate.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages495-498
Number of pages4
ISBN (Electronic)0780376595
DOIs
Publication statusPublished - 2003 Jan 1
EventAsia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan
Duration: 2003 Jan 212003 Jan 24

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2003-January

Other

OtherAsia and South Pacific Design Automation Conference, ASP-DAC 2003
CountryJapan
CityKitakyushu
Period03-01-2103-01-24

Fingerprint

Cryptography
Data storage equipment
Clocks

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Sun, M. C., Su, C. P., Huang, C. T., & Wu, C. W. (2003). Design of a scalable RSA and ECC crypto-processor. In Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference (pp. 495-498). [1195066] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2003-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2003.1195066
Sun, Ming Cheng ; Su, Chih Pin ; Huang, Chih Tsun ; Wu, Cheng Wen. / Design of a scalable RSA and ECC crypto-processor. Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 495-498 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).
@inproceedings{e78e05203bfb4ae59872336a200e453c,
title = "Design of a scalable RSA and ECC crypto-processor",
abstract = "In this paper, we propose a scalable word-based crypto-processor that performs modular multiplication based on the modified Montgomery algorithm for finite fields GF(P) and GF(2m). The unified crypto-processor supports scalable keys of length up to 2048 bits for RSA and 512 bits for elliptic curve cryptography (ECC). Further extension of the key length can be done easily by enlarging the memory module or using the external memory resource. With the proposed parity prediction technique, our pipelined crypto-processor achieves a 512-bit RSA encryption rate of 276 kbps and a 160-bit ECC encryption rate of 73.3 kbps for a 220 MHz clock rate.",
author = "Sun, {Ming Cheng} and Su, {Chih Pin} and Huang, {Chih Tsun} and Wu, {Cheng Wen}",
year = "2003",
month = "1",
day = "1",
doi = "10.1109/ASPDAC.2003.1195066",
language = "English",
series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "495--498",
booktitle = "Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference",
address = "United States",

}

Sun, MC, Su, CP, Huang, CT & Wu, CW 2003, Design of a scalable RSA and ECC crypto-processor. in Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference., 1195066, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 2003-January, Institute of Electrical and Electronics Engineers Inc., pp. 495-498, Asia and South Pacific Design Automation Conference, ASP-DAC 2003, Kitakyushu, Japan, 03-01-21. https://doi.org/10.1109/ASPDAC.2003.1195066

Design of a scalable RSA and ECC crypto-processor. / Sun, Ming Cheng; Su, Chih Pin; Huang, Chih Tsun; Wu, Cheng Wen.

Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., 2003. p. 495-498 1195066 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Design of a scalable RSA and ECC crypto-processor

AU - Sun, Ming Cheng

AU - Su, Chih Pin

AU - Huang, Chih Tsun

AU - Wu, Cheng Wen

PY - 2003/1/1

Y1 - 2003/1/1

N2 - In this paper, we propose a scalable word-based crypto-processor that performs modular multiplication based on the modified Montgomery algorithm for finite fields GF(P) and GF(2m). The unified crypto-processor supports scalable keys of length up to 2048 bits for RSA and 512 bits for elliptic curve cryptography (ECC). Further extension of the key length can be done easily by enlarging the memory module or using the external memory resource. With the proposed parity prediction technique, our pipelined crypto-processor achieves a 512-bit RSA encryption rate of 276 kbps and a 160-bit ECC encryption rate of 73.3 kbps for a 220 MHz clock rate.

AB - In this paper, we propose a scalable word-based crypto-processor that performs modular multiplication based on the modified Montgomery algorithm for finite fields GF(P) and GF(2m). The unified crypto-processor supports scalable keys of length up to 2048 bits for RSA and 512 bits for elliptic curve cryptography (ECC). Further extension of the key length can be done easily by enlarging the memory module or using the external memory resource. With the proposed parity prediction technique, our pipelined crypto-processor achieves a 512-bit RSA encryption rate of 276 kbps and a 160-bit ECC encryption rate of 73.3 kbps for a 220 MHz clock rate.

UR - http://www.scopus.com/inward/record.url?scp=84954420123&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84954420123&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2003.1195066

DO - 10.1109/ASPDAC.2003.1195066

M3 - Conference contribution

AN - SCOPUS:84954420123

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 495

EP - 498

BT - Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Sun MC, Su CP, Huang CT, Wu CW. Design of a scalable RSA and ECC crypto-processor. In Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc. 2003. p. 495-498. 1195066. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2003.1195066