Design of a shared buffer management scheme for ATM switches

C. S. Lin, B. D. Liu, Y. C. Tane

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)


This paper presents a novel memory management scheme for shared buffer ATM switch that features low cost, high throughput, and high memory utilization. The design approach is based on the dual-port RAM device which can improve the memory bandwidth and reduce the complex address control of shared buffer. In addition, the proposed memory management scheme adopts a temporary-point approach to improve the conventional bubble elimination design. The temporary-point approach eliminates the bubble problem of linked list chain, as well as achieves double throughput performance compared with conventional single-port RAM shared buffer architecture, The whole design was fabricated with the TSMC 0.35 μm SPQM CMOS process parameters under 3.3 V supply voltage. With a 256 cells shared buffer architecture, the measured results show that both cell-writing process and cell-reading process of this chip worked in parallel with the speed up to 25 MHz.

Original languageEnglish
Title of host publicationProceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
EditorsJohn Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)0780374940
Publication statusPublished - 2002 Jan 1
Event15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States
Duration: 2002 Sept 252002 Sept 28

Publication series

NameProceedings of the Annual IEEE International ASIC Conference and Exhibit
ISSN (Print)1063-0988


Other15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Country/TerritoryUnited States

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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