Design of AND and NAND logic gate using NDR-based circuit suitable for CMOS process

Dong Shong Liang; Cheng-Chi Tai; Kwang Jow Gan; Cher Shiung Tsai; Yaw Hwang Chen

doi:10.1109/APCCAS.2006.342428

Design of AND and NAND logic gate using NDR-based circuit suitable for CMOS process

Dong Shong Liang, Cheng-Chi Tai, Kwang Jow Gan, Cher Shiung Tsai, Yaw Hwang Chen

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

AND and NAND logic gate based on the negative differential resistance (NDR) device is demonstrated. This NDR device is made of metal-oxide-semiconductor field-effect-transistor (MOS) devices that could exhibit the NDR characteristic in the current-voltage curve by suitably arranging the MOS parameters. The devices and circuits are implemented by the standard 0.35μm CMOS process.

Original language	English
Title of host publication	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Pages	1325-1328
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2006.342428
Publication status	Published - 2006 Dec 1
Event	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore Duration: 2006 Dec 4 → 2006 Dec 6

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

Other	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Country/Territory	Singapore
Period	06-12-04 → 06-12-06

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/APCCAS.2006.342428

Cite this

Liang, D. S., Tai, C.-C., Gan, K. J., Tsai, C. S., & Chen, Y. H. (2006). Design of AND and NAND logic gate using NDR-based circuit suitable for CMOS process. In APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems (pp. 1325-1328). Article 4145645 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2006.342428

@inproceedings{8dac48f28ce44df3ae88c9fe692d50e4,

title = "Design of AND and NAND logic gate using NDR-based circuit suitable for CMOS process",

abstract = "AND and NAND logic gate based on the negative differential resistance (NDR) device is demonstrated. This NDR device is made of metal-oxide-semiconductor field-effect-transistor (MOS) devices that could exhibit the NDR characteristic in the current-voltage curve by suitably arranging the MOS parameters. The devices and circuits are implemented by the standard 0.35μm CMOS process.",

author = "Liang, {Dong Shong} and Cheng-Chi Tai and Gan, {Kwang Jow} and Tsai, {Cher Shiung} and Chen, {Yaw Hwang}",

year = "2006",

month = dec,

day = "1",

doi = "10.1109/APCCAS.2006.342428",

language = "English",

isbn = "1424403871",

series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",

pages = "1325--1328",

booktitle = "APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems",

note = "APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems ; Conference date: 04-12-2006 Through 06-12-2006",

}

Liang, DS, Tai, C-C, Gan, KJ, Tsai, CS & Chen, YH 2006, Design of AND and NAND logic gate using NDR-based circuit suitable for CMOS process. in APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems., 4145645, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 1325-1328, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, Singapore, 06-12-04. https://doi.org/10.1109/APCCAS.2006.342428

Design of AND and NAND logic gate using NDR-based circuit suitable for CMOS process. / Liang, Dong Shong; Tai, Cheng-Chi; Gan, Kwang Jow et al.
APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. 2006. p. 1325-1328 4145645 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Design of AND and NAND logic gate using NDR-based circuit suitable for CMOS process

AU - Liang, Dong Shong

AU - Tai, Cheng-Chi

AU - Gan, Kwang Jow

AU - Tsai, Cher Shiung

AU - Chen, Yaw Hwang

PY - 2006/12/1

Y1 - 2006/12/1

N2 - AND and NAND logic gate based on the negative differential resistance (NDR) device is demonstrated. This NDR device is made of metal-oxide-semiconductor field-effect-transistor (MOS) devices that could exhibit the NDR characteristic in the current-voltage curve by suitably arranging the MOS parameters. The devices and circuits are implemented by the standard 0.35μm CMOS process.

AB - AND and NAND logic gate based on the negative differential resistance (NDR) device is demonstrated. This NDR device is made of metal-oxide-semiconductor field-effect-transistor (MOS) devices that could exhibit the NDR characteristic in the current-voltage curve by suitably arranging the MOS parameters. The devices and circuits are implemented by the standard 0.35μm CMOS process.

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DO - 10.1109/APCCAS.2006.342428

M3 - Conference contribution

AN - SCOPUS:50249105771

SN - 1424403871

SN - 9781424403875

T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

SP - 1325

EP - 1328

BT - APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

T2 - APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

Y2 - 4 December 2006 through 6 December 2006

ER -

Design of AND and NAND logic gate using NDR-based circuit suitable for CMOS process

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