Design of divider circuit for electrochemical impedance spectroscopy measurement system

Siang Wei Wang; Tse An Chen; Kuan Hung Chen; Chia Ling Wei

doi:10.1109/VLSI-DAT.2018.8373225

Design of divider circuit for electrochemical impedance spectroscopy measurement system

Siang Wei Wang, Tse An Chen, Kuan Hung Chen, Chia Ling Wei

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

In an electrochemical impedance spectroscopy (EIS) measurement system, it needs to calculate the amplitude ratio between the reference signal and measured signal, which reqiures a divider. In this work, a chip, which cosists of peak detectors, a divider and other signal processing circuits, was proposed for the EIS measurement system. This chip is capable of obtaining the amplitude ratio of reference to measured signals. The chip was fabricated by using a 0.35μm CMOS/MEMS 2P4M mixed-signal polycide process, and the frequency of the input frequency can range from 10 Hz to 10 kHz.

Original language	English
Title of host publication	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-4
Number of pages	4
ISBN (Electronic)	9781538642603
DOIs	https://doi.org/10.1109/VLSI-DAT.2018.8373225
Publication status	Published - 2018 Jun 5
Event	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 - Hsinchu, Taiwan Duration: 2018 Apr 16 → 2018 Apr 19

Publication series

Name	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

Other

Other	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
Country/Territory	Taiwan
City	Hsinchu
Period	18-04-16 → 18-04-19

All Science Journal Classification (ASJC) codes

Safety, Risk, Reliability and Quality
Control and Optimization
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/VLSI-DAT.2018.8373225

Cite this

Wang, S. W., Chen, T. A., Chen, K. H., & Wei, C. L. (2018). Design of divider circuit for electrochemical impedance spectroscopy measurement system. In 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 (pp. 1-4). (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2018.8373225

Wang, Siang Wei ; Chen, Tse An ; Chen, Kuan Hung et al. / Design of divider circuit for electrochemical impedance spectroscopy measurement system. 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 1-4 (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018).

@inproceedings{cad1b28586dd45f596fc15e3d948bdb6,

title = "Design of divider circuit for electrochemical impedance spectroscopy measurement system",

abstract = "In an electrochemical impedance spectroscopy (EIS) measurement system, it needs to calculate the amplitude ratio between the reference signal and measured signal, which reqiures a divider. In this work, a chip, which cosists of peak detectors, a divider and other signal processing circuits, was proposed for the EIS measurement system. This chip is capable of obtaining the amplitude ratio of reference to measured signals. The chip was fabricated by using a 0.35μm CMOS/MEMS 2P4M mixed-signal polycide process, and the frequency of the input frequency can range from 10 Hz to 10 kHz.",

author = "Wang, {Siang Wei} and Chen, {Tse An} and Chen, {Kuan Hung} and Wei, {Chia Ling}",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 ; Conference date: 16-04-2018 Through 19-04-2018",

year = "2018",

month = jun,

day = "5",

doi = "10.1109/VLSI-DAT.2018.8373225",

language = "English",

series = "2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1--4",

booktitle = "2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018",

address = "United States",

}

Wang, SW, Chen, TA, Chen, KH & Wei, CL 2018, Design of divider circuit for electrochemical impedance spectroscopy measurement system. in 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018, Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018, Hsinchu, Taiwan, 18-04-16. https://doi.org/10.1109/VLSI-DAT.2018.8373225

Design of divider circuit for electrochemical impedance spectroscopy measurement system. / Wang, Siang Wei; Chen, Tse An; Chen, Kuan Hung et al.
2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-4 (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Design of divider circuit for electrochemical impedance spectroscopy measurement system

AU - Wang, Siang Wei

AU - Chen, Tse An

AU - Chen, Kuan Hung

AU - Wei, Chia Ling

PY - 2018/6/5

Y1 - 2018/6/5

N2 - In an electrochemical impedance spectroscopy (EIS) measurement system, it needs to calculate the amplitude ratio between the reference signal and measured signal, which reqiures a divider. In this work, a chip, which cosists of peak detectors, a divider and other signal processing circuits, was proposed for the EIS measurement system. This chip is capable of obtaining the amplitude ratio of reference to measured signals. The chip was fabricated by using a 0.35μm CMOS/MEMS 2P4M mixed-signal polycide process, and the frequency of the input frequency can range from 10 Hz to 10 kHz.

AB - In an electrochemical impedance spectroscopy (EIS) measurement system, it needs to calculate the amplitude ratio between the reference signal and measured signal, which reqiures a divider. In this work, a chip, which cosists of peak detectors, a divider and other signal processing circuits, was proposed for the EIS measurement system. This chip is capable of obtaining the amplitude ratio of reference to measured signals. The chip was fabricated by using a 0.35μm CMOS/MEMS 2P4M mixed-signal polycide process, and the frequency of the input frequency can range from 10 Hz to 10 kHz.

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DO - 10.1109/VLSI-DAT.2018.8373225

M3 - Conference contribution

AN - SCOPUS:85049355323

T3 - 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

SP - 1

EP - 4

BT - 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

Y2 - 16 April 2018 through 19 April 2018

ER -

Wang SW, Chen TA, Chen KH, Wei CL. Design of divider circuit for electrochemical impedance spectroscopy measurement system. In 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-4. (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018). doi: 10.1109/VLSI-DAT.2018.8373225

Design of divider circuit for electrochemical impedance spectroscopy measurement system

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