TY - JOUR
T1 - Design of dynamic voltage restorer with disturbance-filtering enhancement
AU - Huang, Chi Jen
AU - Huang, Shyh Jier
AU - Pai, Fu Sheng
N1 - Funding Information:
Manuscript received August 14, 2002; revised March 10, 2003. This work was supported by the National Science Council, R.O.C., under Contract NSC90-2213-E-006-103. Recommended by Associate Editor J. H. R. Enslin. C.-J. Huang and F.-S. Pai are with the Department of Electrical Engineering, Kun Shan University of Technology, Tainan, Taiwan 710, R.O.C. S.-J. Huang is with the Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan 70101, R.O.C. (e-mail: [email protected]). Digital Object Identifier 10.1109/TPEL.2003.816192
PY - 2003/9
Y1 - 2003/9
N2 - In this paper, a new approach for the design of dynamic voltage restorer is proposed. By installing the filtering scheme at utility side and load side, the designated dynamic voltage restorer not only effectively compensates the voltage disturbances, but also helps ensure the supplying power quality. To validate the effectiveness of the method, several disturbance scenarios including voltage sag, oscillatory transients and power surges were examined in the simulation study. This is further supported through the hardware realization of the proposed design, where experimental results obtained under load change and voltage distortion scenarios were both investigated. Test results revealed that the proposed method is able to withstand possible disturbances at a faster dynamic response, thereby consolidating the feasibility and practicality of the approach for the applications considered.
AB - In this paper, a new approach for the design of dynamic voltage restorer is proposed. By installing the filtering scheme at utility side and load side, the designated dynamic voltage restorer not only effectively compensates the voltage disturbances, but also helps ensure the supplying power quality. To validate the effectiveness of the method, several disturbance scenarios including voltage sag, oscillatory transients and power surges were examined in the simulation study. This is further supported through the hardware realization of the proposed design, where experimental results obtained under load change and voltage distortion scenarios were both investigated. Test results revealed that the proposed method is able to withstand possible disturbances at a faster dynamic response, thereby consolidating the feasibility and practicality of the approach for the applications considered.
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U2 - 10.1109/TPEL.2003.816192
DO - 10.1109/TPEL.2003.816192
M3 - Article
AN - SCOPUS:0141787913
SN - 0885-8993
VL - 18
SP - 1202
EP - 1210
JO - IEEE Transactions on Power Electronics
JF - IEEE Transactions on Power Electronics
IS - 5
ER -