Design of easily testable VLSI arrays for discrete cosine transform

Shyue Kung Lu, Cheng Wen Wu, Sy Yen Kuo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A design-for-testability approach based on die M-testability conditions is applied to the bit-level VLSI systolic arrays for discrete cosine transform (DCT). Our M-testability conditions guarantee 100% single-cellfault testability with a minimum number of test patterns. A hardware overhead of no more than 6% is sufficient to make the DCT arrays M-testable. The resulting number of test patterns is only 16, regardless of the size of the DCT array and the internal word length. Apart from the cell-fault model, we also discuss the DCT array testing using die module-fault model. This method detects all possible combinational module faults pseudoexhaustively. Since practical DCT arrays can be quite large, diagnosis for the array is considered important. We propose an off-line fault diagnosis scheme which detects and locates any faulty module by a self-comparison approach.

Original languageEnglish
Title of host publicationConference Record of the 26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992
PublisherIEEE Computer Society
Pages989-993
Number of pages5
ISBN (Electronic)0818631600
DOIs
Publication statusPublished - 1992 Jan 1
Event26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992 - Pacific Grove, United States
Duration: 1992 Oct 261992 Oct 28

Publication series

NameConference Record - Asilomar Conference on Signals, Systems and Computers
ISSN (Print)1058-6393

Conference

Conference26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992
CountryUnited States
CityPacific Grove
Period92-10-2692-10-28

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Networks and Communications

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