TY - GEN
T1 - Design of FinFET SRAM cells using a statistical compact model
AU - Lu, Darsen D.
AU - Lin, Chung Hsun
AU - Yao, Shijing
AU - Xiong, Weize
AU - Bauer, Florian
AU - Cleavelin, Cloves R.
AU - Niknejad, Ali M.
AU - Hu, Chenming
PY - 2009
Y1 - 2009
N2 - A study of designing FinFET-based SRAM cells using a compact model is reported. Parameters for a multi-gate FET compact model, BSIM-MG are extracted from fabricated n-type and p-type SOI FinFETs. Local mismatch in gate length and fin width is calibrated to electrical measurements of 378 FinFET SRAM cells. The cell design is re-optimized through Monte Carlo statistical simulations. Variation in readability, writability and static leakage of the cell are studied.
AB - A study of designing FinFET-based SRAM cells using a compact model is reported. Parameters for a multi-gate FET compact model, BSIM-MG are extracted from fabricated n-type and p-type SOI FinFETs. Local mismatch in gate length and fin width is calibrated to electrical measurements of 378 FinFET SRAM cells. The cell design is re-optimized through Monte Carlo statistical simulations. Variation in readability, writability and static leakage of the cell are studied.
UR - http://www.scopus.com/inward/record.url?scp=74349127359&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=74349127359&partnerID=8YFLogxK
U2 - 10.1109/SISPAD.2009.5290234
DO - 10.1109/SISPAD.2009.5290234
M3 - Conference contribution
AN - SCOPUS:74349127359
SN - 9781424439492
T3 - International Conference on Simulation of Semiconductor Processes and Devices, SISPAD
BT - SISPAD 2009 - 2009 International Conference on Simulation of Semiconductor Processes and Devices
T2 - SISPAD 2009 - 2009 International Conference on Simulation of Semiconductor Processes and Devices
Y2 - 9 September 2009 through 11 September 2009
ER -