Design of high-speed bit-serial divider in GF(2m)

Wen Ching Lin, Ming-Der Shieh, Chien Ming Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

In this paper, we reformulated the conventional iterative division algorithm by substituting the pre-defined variable and then updating its initial value accordingly. The reformulated division algorithm allows a restructuring of the divider architecture to further improve its operating speed without increasing latency and area cost. Using the proposed fast algorithm, we developed a high-speed bit-serial GF(2m) divider. Analytical results show that the cost of the initial value update and variable transformation in the reformulated algorithm is almost negligible in the hardware implementation. Our divider reduces the critical path delay. Compared with related divider designs, the proposed design has time and area advantages.

Original languageEnglish
Title of host publicationISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publicationNano-Bio Circuit Fabrics and Systems
Pages713-716
Number of pages4
DOIs
Publication statusPublished - 2010
Event2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France
Duration: 2010 May 302010 Jun 2

Other

Other2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
CountryFrance
CityParis
Period10-05-3010-06-02

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Costs
Hardware

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Lin, W. C., Shieh, M-D., & Wu, C. M. (2010). Design of high-speed bit-serial divider in GF(2m). In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 713-716). [5537479] https://doi.org/10.1109/ISCAS.2010.5537479
Lin, Wen Ching ; Shieh, Ming-Der ; Wu, Chien Ming. / Design of high-speed bit-serial divider in GF(2m). ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. pp. 713-716
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Lin, WC, Shieh, M-D & Wu, CM 2010, Design of high-speed bit-serial divider in GF(2m). in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537479, pp. 713-716, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, France, 10-05-30. https://doi.org/10.1109/ISCAS.2010.5537479

Design of high-speed bit-serial divider in GF(2m). / Lin, Wen Ching; Shieh, Ming-Der; Wu, Chien Ming.

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 713-716 5537479.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - In this paper, we reformulated the conventional iterative division algorithm by substituting the pre-defined variable and then updating its initial value accordingly. The reformulated division algorithm allows a restructuring of the divider architecture to further improve its operating speed without increasing latency and area cost. Using the proposed fast algorithm, we developed a high-speed bit-serial GF(2m) divider. Analytical results show that the cost of the initial value update and variable transformation in the reformulated algorithm is almost negligible in the hardware implementation. Our divider reduces the critical path delay. Compared with related divider designs, the proposed design has time and area advantages.

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Lin WC, Shieh M-D, Wu CM. Design of high-speed bit-serial divider in GF(2m). In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 713-716. 5537479 https://doi.org/10.1109/ISCAS.2010.5537479