Abstract
In this paper, we reformulated the conventional iterative division algorithm by substituting the pre-defined variable and then updating its initial value accordingly. The reformulated division algorithm allows a restructuring of the divider architecture to further improve its operating speed without increasing latency and area cost. Using the proposed fast algorithm, we developed a high-speed bit-serial GF(2m) divider. Analytical results show that the cost of the initial value update and variable transformation in the reformulated algorithm is almost negligible in the hardware implementation. Our divider reduces the critical path delay. Compared with related divider designs, the proposed design has time and area advantages.
| Original language | English |
|---|---|
| Title of host publication | ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems |
| Subtitle of host publication | Nano-Bio Circuit Fabrics and Systems |
| Pages | 713-716 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2010 |
| Event | 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France Duration: 2010 May 30 → 2010 Jun 2 |
Other
| Other | 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 |
|---|---|
| Country | France |
| City | Paris |
| Period | 10-05-30 → 10-06-02 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
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Design of high-speed bit-serial divider in GF(2m). / Lin, Wen Ching; Shieh, Ming-Der; Wu, Chien Ming.
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 713-716 5537479.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Design of high-speed bit-serial divider in GF(2m)
AU - Lin, Wen Ching
AU - Shieh, Ming-Der
AU - Wu, Chien Ming
PY - 2010
Y1 - 2010
N2 - In this paper, we reformulated the conventional iterative division algorithm by substituting the pre-defined variable and then updating its initial value accordingly. The reformulated division algorithm allows a restructuring of the divider architecture to further improve its operating speed without increasing latency and area cost. Using the proposed fast algorithm, we developed a high-speed bit-serial GF(2m) divider. Analytical results show that the cost of the initial value update and variable transformation in the reformulated algorithm is almost negligible in the hardware implementation. Our divider reduces the critical path delay. Compared with related divider designs, the proposed design has time and area advantages.
AB - In this paper, we reformulated the conventional iterative division algorithm by substituting the pre-defined variable and then updating its initial value accordingly. The reformulated division algorithm allows a restructuring of the divider architecture to further improve its operating speed without increasing latency and area cost. Using the proposed fast algorithm, we developed a high-speed bit-serial GF(2m) divider. Analytical results show that the cost of the initial value update and variable transformation in the reformulated algorithm is almost negligible in the hardware implementation. Our divider reduces the critical path delay. Compared with related divider designs, the proposed design has time and area advantages.
UR - http://www.scopus.com/inward/record.url?scp=77956008609&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77956008609&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2010.5537479
DO - 10.1109/ISCAS.2010.5537479
M3 - Conference contribution
SN - 9781424453085
SP - 713
EP - 716
BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
ER -