Design of high-speed bit-serial divider in GF(2m)

Wen Ching Lin; Ming-Der Shieh; Chien Ming Wu

doi:10.1109/ISCAS.2010.5537479

Design of high-speed bit-serial divider in GF(2^m)

Wen Ching Lin, Ming-Der Shieh, Chien Ming Wu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

In this paper, we reformulated the conventional iterative division algorithm by substituting the pre-defined variable and then updating its initial value accordingly. The reformulated division algorithm allows a restructuring of the divider architecture to further improve its operating speed without increasing latency and area cost. Using the proposed fast algorithm, we developed a high-speed bit-serial GF(2^m) divider. Analytical results show that the cost of the initial value update and variable transformation in the reformulated algorithm is almost negligible in the hardware implementation. Our divider reduces the critical path delay. Compared with related divider designs, the proposed design has time and area advantages.

Original language	English
Title of host publication	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publication	Nano-Bio Circuit Fabrics and Systems
Pages	713-716
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2010.5537479
Publication status	Published - 2010 Aug 31
Event	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France Duration: 2010 May 30 → 2010 Jun 2

Publication series

Name	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Other

Other	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Country/Territory	France
City	Paris
Period	10-05-30 → 10-06-02

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2010.5537479

Cite this

Lin, W. C., Shieh, M-D., & Wu, C. M. (2010). Design of high-speed bit-serial divider in GF(2^m). In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 713-716). [5537479] (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537479

@inproceedings{5b04265dc6734d74abfa4d2265f37a37,

title = "Design of high-speed bit-serial divider in GF(2m)",

abstract = "In this paper, we reformulated the conventional iterative division algorithm by substituting the pre-defined variable and then updating its initial value accordingly. The reformulated division algorithm allows a restructuring of the divider architecture to further improve its operating speed without increasing latency and area cost. Using the proposed fast algorithm, we developed a high-speed bit-serial GF(2m) divider. Analytical results show that the cost of the initial value update and variable transformation in the reformulated algorithm is almost negligible in the hardware implementation. Our divider reduces the critical path delay. Compared with related divider designs, the proposed design has time and area advantages.",

author = "Lin, {Wen Ching} and Ming-Der Shieh and Wu, {Chien Ming}",

year = "2010",

month = aug,

day = "31",

doi = "10.1109/ISCAS.2010.5537479",

language = "English",

isbn = "9781424453085",

series = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems",

pages = "713--716",

booktitle = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems",

note = "2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 ; Conference date: 30-05-2010 Through 02-06-2010",

}

Lin, WC, Shieh, M-D & Wu, CM 2010, Design of high-speed bit-serial divider in GF(2^m). in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537479, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, pp. 713-716, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, France, 10-05-30. https://doi.org/10.1109/ISCAS.2010.5537479

Design of high-speed bit-serial divider in GF(2^m). / Lin, Wen Ching; Shieh, Ming-Der; Wu, Chien Ming.

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 713-716 5537479 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Design of high-speed bit-serial divider in GF(2m)

AU - Lin, Wen Ching

AU - Shieh, Ming-Der

AU - Wu, Chien Ming

PY - 2010/8/31

Y1 - 2010/8/31

N2 - In this paper, we reformulated the conventional iterative division algorithm by substituting the pre-defined variable and then updating its initial value accordingly. The reformulated division algorithm allows a restructuring of the divider architecture to further improve its operating speed without increasing latency and area cost. Using the proposed fast algorithm, we developed a high-speed bit-serial GF(2m) divider. Analytical results show that the cost of the initial value update and variable transformation in the reformulated algorithm is almost negligible in the hardware implementation. Our divider reduces the critical path delay. Compared with related divider designs, the proposed design has time and area advantages.

AB - In this paper, we reformulated the conventional iterative division algorithm by substituting the pre-defined variable and then updating its initial value accordingly. The reformulated division algorithm allows a restructuring of the divider architecture to further improve its operating speed without increasing latency and area cost. Using the proposed fast algorithm, we developed a high-speed bit-serial GF(2m) divider. Analytical results show that the cost of the initial value update and variable transformation in the reformulated algorithm is almost negligible in the hardware implementation. Our divider reduces the critical path delay. Compared with related divider designs, the proposed design has time and area advantages.

UR - http://www.scopus.com/inward/record.url?scp=77956008609&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77956008609&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2010.5537479

DO - 10.1109/ISCAS.2010.5537479

M3 - Conference contribution

AN - SCOPUS:77956008609

SN - 9781424453085

T3 - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

SP - 713

EP - 716

BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems

T2 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010

Y2 - 30 May 2010 through 2 June 2010

ER -

Lin WC, Shieh M-D, Wu CM. Design of high-speed bit-serial divider in GF(2^m). In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 713-716. 5537479. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537479