Design of high-speed errors-and-erasures reed-solomon decoders for multi-mode applications

Yung Kuei Lu; Ming-Der Shieh; Wen Hsuen Kuo

doi:10.1109/VDAT.2009.5158129

Design of high-speed errors-and-erasures reed-solomon decoders for multi-mode applications

Yung Kuei Lu, Ming-Der Shieh, Wen Hsuen Kuo

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

A multi-mode Reed-Solomon (RS) decoder design based on the reformulated inversionless Berlekamp-Massey (riBM) algorithm is proposed to correct both errors and erasures for any RS code including shortened codes. Without degrading the resulting performance, we effectively improve the hardware utilization of decoder and simplify the routing network in conventional multi-mode decoder design. With the developed multi-mode arrangement, the proposed decoder possesses not only high-performance property but also simple and regular interconnect topology, making the decoder suitable for VLSI realization. Experimental results reveal that for code words of length n < 255 with v errors and ρ erasures correcting capability, 0< 2v+ρ < 16, the achievable throughput rate of the proposed decoder, implemented in TSMC 0.13μam 1P8M process, is 4Gbps at a maximum operating clock of 450MHz and the total gate count is 50K.

Original language	English
Title of host publication	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Pages	199-202
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2009.5158129
Publication status	Published - 2009
Event	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan Duration: 2009 Apr 28 → 2009 Apr 30

Other

Other	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Country/Territory	Taiwan
City	Hsinchu
Period	09-04-28 → 09-04-30

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

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10.1109/VDAT.2009.5158129

Cite this

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title = "Design of high-speed errors-and-erasures reed-solomon decoders for multi-mode applications",

abstract = "A multi-mode Reed-Solomon (RS) decoder design based on the reformulated inversionless Berlekamp-Massey (riBM) algorithm is proposed to correct both errors and erasures for any RS code including shortened codes. Without degrading the resulting performance, we effectively improve the hardware utilization of decoder and simplify the routing network in conventional multi-mode decoder design. With the developed multi-mode arrangement, the proposed decoder possesses not only high-performance property but also simple and regular interconnect topology, making the decoder suitable for VLSI realization. Experimental results reveal that for code words of length n < 255 with v errors and ρ erasures correcting capability, 0< 2v+ρ < 16, the achievable throughput rate of the proposed decoder, implemented in TSMC 0.13μam 1P8M process, is 4Gbps at a maximum operating clock of 450MHz and the total gate count is 50K.",

author = "Lu, {Yung Kuei} and Ming-Der Shieh and Kuo, {Wen Hsuen}",

year = "2009",

doi = "10.1109/VDAT.2009.5158129",

language = "English",

isbn = "9781424427826",

pages = "199--202",

booktitle = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09",

note = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 ; Conference date: 28-04-2009 Through 30-04-2009",

}

Lu, YK, Shieh, M-D & Kuo, WH 2009, Design of high-speed errors-and-erasures reed-solomon decoders for multi-mode applications. in 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09., 5158129, pp. 199-202, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, Hsinchu, Taiwan, 09-04-28. https://doi.org/10.1109/VDAT.2009.5158129

TY - GEN

T1 - Design of high-speed errors-and-erasures reed-solomon decoders for multi-mode applications

AU - Lu, Yung Kuei

AU - Shieh, Ming-Der

AU - Kuo, Wen Hsuen

PY - 2009

Y1 - 2009

N2 - A multi-mode Reed-Solomon (RS) decoder design based on the reformulated inversionless Berlekamp-Massey (riBM) algorithm is proposed to correct both errors and erasures for any RS code including shortened codes. Without degrading the resulting performance, we effectively improve the hardware utilization of decoder and simplify the routing network in conventional multi-mode decoder design. With the developed multi-mode arrangement, the proposed decoder possesses not only high-performance property but also simple and regular interconnect topology, making the decoder suitable for VLSI realization. Experimental results reveal that for code words of length n < 255 with v errors and ρ erasures correcting capability, 0< 2v+ρ < 16, the achievable throughput rate of the proposed decoder, implemented in TSMC 0.13μam 1P8M process, is 4Gbps at a maximum operating clock of 450MHz and the total gate count is 50K.

AB - A multi-mode Reed-Solomon (RS) decoder design based on the reformulated inversionless Berlekamp-Massey (riBM) algorithm is proposed to correct both errors and erasures for any RS code including shortened codes. Without degrading the resulting performance, we effectively improve the hardware utilization of decoder and simplify the routing network in conventional multi-mode decoder design. With the developed multi-mode arrangement, the proposed decoder possesses not only high-performance property but also simple and regular interconnect topology, making the decoder suitable for VLSI realization. Experimental results reveal that for code words of length n < 255 with v errors and ρ erasures correcting capability, 0< 2v+ρ < 16, the achievable throughput rate of the proposed decoder, implemented in TSMC 0.13μam 1P8M process, is 4Gbps at a maximum operating clock of 450MHz and the total gate count is 50K.

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M3 - Conference contribution

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SN - 9781424427826

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BT - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

T2 - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Y2 - 28 April 2009 through 30 April 2009

ER -

Design of high-speed errors-and-erasures reed-solomon decoders for multi-mode applications

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