Abstract
A multi-mode Reed-Solomon (RS) decoder design based on the reformulated inversionless Berlekamp-Massey (riBM) algorithm is proposed to correct both errors and erasures for any RS code including shortened codes. Without degrading the resulting performance, we effectively improve the hardware utilization of decoder and simplify the routing network in conventional multi-mode decoder design. With the developed multi-mode arrangement, the proposed decoder possesses not only high-performance property but also simple and regular interconnect topology, making the decoder suitable for VLSI realization. Experimental results reveal that for code words of length n < 255 with v errors and ρ erasures correcting capability, 0< 2v+ρ < 16, the achievable throughput rate of the proposed decoder, implemented in TSMC 0.13μam 1P8M process, is 4Gbps at a maximum operating clock of 450MHz and the total gate count is 50K.
| Original language | English |
|---|---|
| Title of host publication | 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 |
| Pages | 199-202 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2009 |
| Event | 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan Duration: 2009 Apr 28 → 2009 Apr 30 |
Other
| Other | 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 |
|---|---|
| Country | Taiwan |
| City | Hsinchu |
| Period | 09-04-28 → 09-04-30 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Control and Systems Engineering
- Electrical and Electronic Engineering
Cite this
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Design of high-speed errors-and-erasures reed-solomon decoders for multi-mode applications. / Lu, Yung Kuei; Shieh, Ming-Der; Kuo, Wen Hsuen.
2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09. 2009. p. 199-202 5158129.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Design of high-speed errors-and-erasures reed-solomon decoders for multi-mode applications
AU - Lu, Yung Kuei
AU - Shieh, Ming-Der
AU - Kuo, Wen Hsuen
PY - 2009
Y1 - 2009
N2 - A multi-mode Reed-Solomon (RS) decoder design based on the reformulated inversionless Berlekamp-Massey (riBM) algorithm is proposed to correct both errors and erasures for any RS code including shortened codes. Without degrading the resulting performance, we effectively improve the hardware utilization of decoder and simplify the routing network in conventional multi-mode decoder design. With the developed multi-mode arrangement, the proposed decoder possesses not only high-performance property but also simple and regular interconnect topology, making the decoder suitable for VLSI realization. Experimental results reveal that for code words of length n < 255 with v errors and ρ erasures correcting capability, 0< 2v+ρ < 16, the achievable throughput rate of the proposed decoder, implemented in TSMC 0.13μam 1P8M process, is 4Gbps at a maximum operating clock of 450MHz and the total gate count is 50K.
AB - A multi-mode Reed-Solomon (RS) decoder design based on the reformulated inversionless Berlekamp-Massey (riBM) algorithm is proposed to correct both errors and erasures for any RS code including shortened codes. Without degrading the resulting performance, we effectively improve the hardware utilization of decoder and simplify the routing network in conventional multi-mode decoder design. With the developed multi-mode arrangement, the proposed decoder possesses not only high-performance property but also simple and regular interconnect topology, making the decoder suitable for VLSI realization. Experimental results reveal that for code words of length n < 255 with v errors and ρ erasures correcting capability, 0< 2v+ρ < 16, the achievable throughput rate of the proposed decoder, implemented in TSMC 0.13μam 1P8M process, is 4Gbps at a maximum operating clock of 450MHz and the total gate count is 50K.
UR - http://www.scopus.com/inward/record.url?scp=77950647621&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77950647621&partnerID=8YFLogxK
U2 - 10.1109/VDAT.2009.5158129
DO - 10.1109/VDAT.2009.5158129
M3 - Conference contribution
SN - 9781424427826
SP - 199
EP - 202
BT - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
ER -