Design of high-speed errors-and-erasures reed-solomon decoders for multi-mode applications

Yung Kuei Lu, Ming-Der Shieh, Wen Hsuen Kuo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A multi-mode Reed-Solomon (RS) decoder design based on the reformulated inversionless Berlekamp-Massey (riBM) algorithm is proposed to correct both errors and erasures for any RS code including shortened codes. Without degrading the resulting performance, we effectively improve the hardware utilization of decoder and simplify the routing network in conventional multi-mode decoder design. With the developed multi-mode arrangement, the proposed decoder possesses not only high-performance property but also simple and regular interconnect topology, making the decoder suitable for VLSI realization. Experimental results reveal that for code words of length n < 255 with v errors and ρ erasures correcting capability, 0< 2v+ρ < 16, the achievable throughput rate of the proposed decoder, implemented in TSMC 0.13μam 1P8M process, is 4Gbps at a maximum operating clock of 450MHz and the total gate count is 50K.

Original languageEnglish
Title of host publication2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Pages199-202
Number of pages4
DOIs
Publication statusPublished - 2009
Event2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan
Duration: 2009 Apr 282009 Apr 30

Other

Other2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
CountryTaiwan
CityHsinchu
Period09-04-2809-04-30

Fingerprint

Reed-Solomon codes
Network routing
Clocks
Throughput
Topology
Hardware

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Lu, Y. K., Shieh, M-D., & Kuo, W. H. (2009). Design of high-speed errors-and-erasures reed-solomon decoders for multi-mode applications. In 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 (pp. 199-202). [5158129] https://doi.org/10.1109/VDAT.2009.5158129
Lu, Yung Kuei ; Shieh, Ming-Der ; Kuo, Wen Hsuen. / Design of high-speed errors-and-erasures reed-solomon decoders for multi-mode applications. 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09. 2009. pp. 199-202
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abstract = "A multi-mode Reed-Solomon (RS) decoder design based on the reformulated inversionless Berlekamp-Massey (riBM) algorithm is proposed to correct both errors and erasures for any RS code including shortened codes. Without degrading the resulting performance, we effectively improve the hardware utilization of decoder and simplify the routing network in conventional multi-mode decoder design. With the developed multi-mode arrangement, the proposed decoder possesses not only high-performance property but also simple and regular interconnect topology, making the decoder suitable for VLSI realization. Experimental results reveal that for code words of length n < 255 with v errors and ρ erasures correcting capability, 0< 2v+ρ < 16, the achievable throughput rate of the proposed decoder, implemented in TSMC 0.13μam 1P8M process, is 4Gbps at a maximum operating clock of 450MHz and the total gate count is 50K.",
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Lu, YK, Shieh, M-D & Kuo, WH 2009, Design of high-speed errors-and-erasures reed-solomon decoders for multi-mode applications. in 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09., 5158129, pp. 199-202, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, Hsinchu, Taiwan, 09-04-28. https://doi.org/10.1109/VDAT.2009.5158129

Design of high-speed errors-and-erasures reed-solomon decoders for multi-mode applications. / Lu, Yung Kuei; Shieh, Ming-Der; Kuo, Wen Hsuen.

2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09. 2009. p. 199-202 5158129.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Lu YK, Shieh M-D, Kuo WH. Design of high-speed errors-and-erasures reed-solomon decoders for multi-mode applications. In 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09. 2009. p. 199-202. 5158129 https://doi.org/10.1109/VDAT.2009.5158129