Design of on-chip bus with OCP interface

Chin Yao Chang, Yi Jiun Chang, Kuen-Jong Lee, Jen Chieh Yeh, Shih Yin Lin, Jui Liang Ma

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

As more and more IP cores are integrated into an SOC design, the communication flow between IP cores has increased drastically and the efficiency of the on-chip bus has become a dominant factor for the performance of a system. The on-chip bus design can be divided into two parts, namely the interface and the internal architecture of the bus. In this work we adopt the well-defined interface standard, the Open Core Protocol (OCP), and focus on the design of the internal bus architecture. We develop an efficient bus architecture to support most advanced bus functionalities defined in OCP, including burst transactions, lock transactions, pipelined transactions, and out-of-order transactions. We first model and design the on-chip bus with transaction level modeling for the consideration of design flexibility and fast simulation speed. We then implement the RTL models of the bus for synthesis and gate-level simulation. Experimental results show that the proposed TLM model is quite efficient for the whole system simulation and the real implementation can significantly save the communication time.

Original languageEnglish
Title of host publicationProceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
Pages211-214
Number of pages4
DOIs
Publication statusPublished - 2010 Nov 8
Event2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 - Hsin Chu, Taiwan
Duration: 2010 Apr 262010 Apr 29

Publication series

NameProceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

Other

Other2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
CountryTaiwan
CityHsin Chu
Period10-04-2610-04-29

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Communication
Intellectual property core

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Chang, C. Y., Chang, Y. J., Lee, K-J., Yeh, J. C., Lin, S. Y., & Ma, J. L. (2010). Design of on-chip bus with OCP interface. In Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 (pp. 211-214). [5496727] (Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010). https://doi.org/10.1109/VDAT.2010.5496727
Chang, Chin Yao ; Chang, Yi Jiun ; Lee, Kuen-Jong ; Yeh, Jen Chieh ; Lin, Shih Yin ; Ma, Jui Liang. / Design of on-chip bus with OCP interface. Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010. 2010. pp. 211-214 (Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010).
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Chang, CY, Chang, YJ, Lee, K-J, Yeh, JC, Lin, SY & Ma, JL 2010, Design of on-chip bus with OCP interface. in Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010., 5496727, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010, pp. 211-214, 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010, Hsin Chu, Taiwan, 10-04-26. https://doi.org/10.1109/VDAT.2010.5496727

Design of on-chip bus with OCP interface. / Chang, Chin Yao; Chang, Yi Jiun; Lee, Kuen-Jong; Yeh, Jen Chieh; Lin, Shih Yin; Ma, Jui Liang.

Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010. 2010. p. 211-214 5496727 (Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Chang CY, Chang YJ, Lee K-J, Yeh JC, Lin SY, Ma JL. Design of on-chip bus with OCP interface. In Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010. 2010. p. 211-214. 5496727. (Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010). https://doi.org/10.1109/VDAT.2010.5496727