Design of pipelined mixed-signal fuzzy logic controller with linguistic hedge modifiers

Chuen Yau Chen; Yuan Ta Hsieh; Bin Da Liu

Design of pipelined mixed-signal fuzzy logic controller with linguistic hedge modifiers

Chuen Yau Chen
, Yuan Ta Hsieh
, Bin Da Liu

Department of Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

2 Citations (Scopus)

Abstract

In this paper, we realize the linguistic hedge fuzzy logic controller in a mixed-signal VLSI design with pipelined clocking strategy. Current-mode approach is adopted in designing the signal processing portions to simplify the circuit complexity; digital circuits are adopted to implement the programmable units. All the designs are performed with HSPICE simulation in level 28 model for a 0.35μm SPQM CMOS process. The pipelined strategy speeds up the inference operation to 0.5M FLIPS. The supply voltage of this system is 3.3V.

Original language	English
Pages	148-151
Number of pages	4
Publication status	Published - 2000
Event	2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems - Tianjin, China Duration: 2000 Dec 4 → 2000 Dec 6

Other

Other	2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems
Country/Territory	China
City	Tianjin
Period	00-12-04 → 00-12-06

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

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title = "Design of pipelined mixed-signal fuzzy logic controller with linguistic hedge modifiers",

abstract = "In this paper, we realize the linguistic hedge fuzzy logic controller in a mixed-signal VLSI design with pipelined clocking strategy. Current-mode approach is adopted in designing the signal processing portions to simplify the circuit complexity; digital circuits are adopted to implement the programmable units. All the designs are performed with HSPICE simulation in level 28 model for a 0.35μm SPQM CMOS process. The pipelined strategy speeds up the inference operation to 0.5M FLIPS. The supply voltage of this system is 3.3V.",

author = "Chen, \{Chuen Yau\} and Hsieh, \{Yuan Ta\} and Liu, \{Bin Da\}",

year = "2000",

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note = "2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems ; Conference date: 04-12-2000 Through 06-12-2000",

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TY - CONF

T1 - Design of pipelined mixed-signal fuzzy logic controller with linguistic hedge modifiers

AU - Chen, Chuen Yau

AU - Hsieh, Yuan Ta

AU - Liu, Bin Da

PY - 2000

Y1 - 2000

N2 - In this paper, we realize the linguistic hedge fuzzy logic controller in a mixed-signal VLSI design with pipelined clocking strategy. Current-mode approach is adopted in designing the signal processing portions to simplify the circuit complexity; digital circuits are adopted to implement the programmable units. All the designs are performed with HSPICE simulation in level 28 model for a 0.35μm SPQM CMOS process. The pipelined strategy speeds up the inference operation to 0.5M FLIPS. The supply voltage of this system is 3.3V.

AB - In this paper, we realize the linguistic hedge fuzzy logic controller in a mixed-signal VLSI design with pipelined clocking strategy. Current-mode approach is adopted in designing the signal processing portions to simplify the circuit complexity; digital circuits are adopted to implement the programmable units. All the designs are performed with HSPICE simulation in level 28 model for a 0.35μm SPQM CMOS process. The pipelined strategy speeds up the inference operation to 0.5M FLIPS. The supply voltage of this system is 3.3V.

UR - https://www.scopus.com/pages/publications/2342634483

UR - https://www.scopus.com/pages/publications/2342634483#tab=citedBy

M3 - Paper

AN - SCOPUS:2342634483

SP - 148

EP - 151

T2 - 2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems

Y2 - 4 December 2000 through 6 December 2000

ER -

Design of pipelined mixed-signal fuzzy logic controller with linguistic hedge modifiers

Abstract

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All Science Journal Classification (ASJC) codes

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