Design of UWB RF receiver front-end with heterogeneous chip integration

Y. C. Lin, R. F. Ye, C. T. Lee, T. S. Horng, L. T. Hwang, J. M. Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

In this work, a 3-5 GHz CMOS UWB RF receiver front-end design is described. The design was realized using integrated passive device (IPD) package format as system-in-package (SiP) application. The CMOS circuit consists of a fully differential common gate-low noise amplifier (CG-LNA), an IQ downconversion mixer, and a variable gain amplifier. Three low loss IPD transformer baluns are used to convert unbalanced signals into balanced signals for feeding into the RF and LO input ports of the CMOS circuit. Measurement results indicate that the average conversion gain is 16.3 dB while the average IIP3 and noise figure are around 10.4 dBm and 6.1 dB, respectively, over the entire operating frequency range.

Original languageEnglish
Title of host publicationAsia-Pacific Microwave Conference Proceedings, APMC 2011
Pages347-350
Number of pages4
Publication statusPublished - 2011 Dec 1
EventAsia-Pacific Microwave Conference, APMC 2011 - Melbourne, VIC, Australia
Duration: 2011 Dec 52011 Dec 8

Publication series

NameAsia-Pacific Microwave Conference Proceedings, APMC

Other

OtherAsia-Pacific Microwave Conference, APMC 2011
CountryAustralia
CityMelbourne, VIC
Period11-12-0511-12-08

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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