Design of UWB RF receiver front-end with heterogeneous chip integration

Y. C. Lin; R. F. Ye; C. T. Lee; T. S. Horng; L. T. Hwang; J. M. Wu

Design of UWB RF receiver front-end with heterogeneous chip integration

Y. C. Lin, R. F. Ye, C. T. Lee, T. S. Horng, L. T. Hwang, J. M. Wu

Department of Photonics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

In this work, a 3-5 GHz CMOS UWB RF receiver front-end design is described. The design was realized using integrated passive device (IPD) package format as system-in-package (SiP) application. The CMOS circuit consists of a fully differential common gate-low noise amplifier (CG-LNA), an IQ downconversion mixer, and a variable gain amplifier. Three low loss IPD transformer baluns are used to convert unbalanced signals into balanced signals for feeding into the RF and LO input ports of the CMOS circuit. Measurement results indicate that the average conversion gain is 16.3 dB while the average IIP3 and noise figure are around 10.4 dBm and 6.1 dB, respectively, over the entire operating frequency range.

Original language	English
Title of host publication	Asia-Pacific Microwave Conference Proceedings, APMC 2011
Pages	347-350
Number of pages	4
Publication status	Published - 2011 Dec 1
Event	Asia-Pacific Microwave Conference, APMC 2011 - Melbourne, VIC, Australia Duration: 2011 Dec 5 → 2011 Dec 8

Publication series

Name	Asia-Pacific Microwave Conference Proceedings, APMC

Other

Other	Asia-Pacific Microwave Conference, APMC 2011
Country	Australia
City	Melbourne, VIC
Period	11-12-05 → 11-12-08

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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Cite this

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title = "Design of UWB RF receiver front-end with heterogeneous chip integration",

abstract = "In this work, a 3-5 GHz CMOS UWB RF receiver front-end design is described. The design was realized using integrated passive device (IPD) package format as system-in-package (SiP) application. The CMOS circuit consists of a fully differential common gate-low noise amplifier (CG-LNA), an IQ downconversion mixer, and a variable gain amplifier. Three low loss IPD transformer baluns are used to convert unbalanced signals into balanced signals for feeding into the RF and LO input ports of the CMOS circuit. Measurement results indicate that the average conversion gain is 16.3 dB while the average IIP3 and noise figure are around 10.4 dBm and 6.1 dB, respectively, over the entire operating frequency range.",

author = "Lin, {Y. C.} and Ye, {R. F.} and Lee, {C. T.} and Horng, {T. S.} and Hwang, {L. T.} and Wu, {J. M.}",

year = "2011",

month = dec,

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series = "Asia-Pacific Microwave Conference Proceedings, APMC",

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note = "Asia-Pacific Microwave Conference, APMC 2011 ; Conference date: 05-12-2011 Through 08-12-2011",

}

Design of UWB RF receiver front-end with heterogeneous chip integration. / Lin, Y. C.; Ye, R. F.; Lee, C. T.; Horng, T. S.; Hwang, L. T.; Wu, J. M.

Asia-Pacific Microwave Conference Proceedings, APMC 2011. 2011. p. 347-350 6173757 (Asia-Pacific Microwave Conference Proceedings, APMC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Lin, Y. C.

AU - Ye, R. F.

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AU - Wu, J. M.

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N2 - In this work, a 3-5 GHz CMOS UWB RF receiver front-end design is described. The design was realized using integrated passive device (IPD) package format as system-in-package (SiP) application. The CMOS circuit consists of a fully differential common gate-low noise amplifier (CG-LNA), an IQ downconversion mixer, and a variable gain amplifier. Three low loss IPD transformer baluns are used to convert unbalanced signals into balanced signals for feeding into the RF and LO input ports of the CMOS circuit. Measurement results indicate that the average conversion gain is 16.3 dB while the average IIP3 and noise figure are around 10.4 dBm and 6.1 dB, respectively, over the entire operating frequency range.

AB - In this work, a 3-5 GHz CMOS UWB RF receiver front-end design is described. The design was realized using integrated passive device (IPD) package format as system-in-package (SiP) application. The CMOS circuit consists of a fully differential common gate-low noise amplifier (CG-LNA), an IQ downconversion mixer, and a variable gain amplifier. Three low loss IPD transformer baluns are used to convert unbalanced signals into balanced signals for feeding into the RF and LO input ports of the CMOS circuit. Measurement results indicate that the average conversion gain is 16.3 dB while the average IIP3 and noise figure are around 10.4 dBm and 6.1 dB, respectively, over the entire operating frequency range.

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