A reliability-based design optimization (RBDO) procedure that incorporates sequential optimization and reliability assessment (SORA) algorithm with numerical finite element (FE) simulations is developed for performing interconnect reliability based multi-objective design optimization for a wafer level package (WLP). In this procedure, the board-level temperature cycling (T/C) reliability associated to the fatigue cracking of the solder joints and redistribution layer (RDL) Cu traces is considered as the objective of the design optimization. Effects of uncertainties in geometry tolerances and fatigue life distributions are also considered. Optimizations of the WLP interconnect geometries including RDL Cu pad diameter, pad opening diameter and polymer dielectric thickness were conducted with either minimizing the fatigue damage parameters or maximizing the first-fail life as the objective. It was found that the multi-objective optimization process using the damage parameters associated to individual failure modes may result in target geometries different from the optimization for the failure life.