Design optimization for wafer level package by using sequential optimization and reliability assessment method

Jung Chuan Chien, Tz-Cheng Chiu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A reliability-based design optimization (RBDO) procedure that incorporates sequential optimization and reliability assessment (SORA) algorithm with numerical finite element (FE) simulations is developed for performing interconnect reliability based multi-objective design optimization for a wafer level package (WLP). In this procedure, the board-level temperature cycling (T/C) reliability associated to the fatigue cracking of the solder joints and redistribution layer (RDL) Cu traces is considered as the objective of the design optimization. Effects of uncertainties in geometry tolerances and fatigue life distributions are also considered. Optimizations of the WLP interconnect geometries including RDL Cu pad diameter, pad opening diameter and polymer dielectric thickness were conducted with either minimizing the fatigue damage parameters or maximizing the first-fail life as the objective. It was found that the multi-objective optimization process using the damage parameters associated to individual failure modes may result in target geometries different from the optimization for the failure life.

Original languageEnglish
Title of host publication11th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2016 - Proceedings
PublisherIEEE Computer Society
Pages184-187
Number of pages4
ISBN (Electronic)9781509047697
DOIs
Publication statusPublished - 2016 Dec 27
Event11th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2016 - Taipei, Taiwan
Duration: 2016 Oct 262016 Oct 28

Publication series

NameProceedings of Technical Papers - International Microsystems, Packaging, Assembly, and Circuits Technology Conference, IMPACT
ISSN (Print)2150-5934
ISSN (Electronic)2150-5942

Other

Other11th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2016
CountryTaiwan
CityTaipei
Period16-10-2616-10-28

Fingerprint

Geometry
Fatigue of materials
Fatigue damage
Multiobjective optimization
Soldering alloys
Failure modes
Design optimization
Polymers
Temperature
Uncertainty

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Chien, J. C., & Chiu, T-C. (2016). Design optimization for wafer level package by using sequential optimization and reliability assessment method. In 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2016 - Proceedings (pp. 184-187). [7800049] (Proceedings of Technical Papers - International Microsystems, Packaging, Assembly, and Circuits Technology Conference, IMPACT). IEEE Computer Society. https://doi.org/10.1109/IMPACT.2016.7800049
Chien, Jung Chuan ; Chiu, Tz-Cheng. / Design optimization for wafer level package by using sequential optimization and reliability assessment method. 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2016 - Proceedings. IEEE Computer Society, 2016. pp. 184-187 (Proceedings of Technical Papers - International Microsystems, Packaging, Assembly, and Circuits Technology Conference, IMPACT).
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Chien, JC & Chiu, T-C 2016, Design optimization for wafer level package by using sequential optimization and reliability assessment method. in 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2016 - Proceedings., 7800049, Proceedings of Technical Papers - International Microsystems, Packaging, Assembly, and Circuits Technology Conference, IMPACT, IEEE Computer Society, pp. 184-187, 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2016, Taipei, Taiwan, 16-10-26. https://doi.org/10.1109/IMPACT.2016.7800049

Design optimization for wafer level package by using sequential optimization and reliability assessment method. / Chien, Jung Chuan; Chiu, Tz-Cheng.

11th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2016 - Proceedings. IEEE Computer Society, 2016. p. 184-187 7800049 (Proceedings of Technical Papers - International Microsystems, Packaging, Assembly, and Circuits Technology Conference, IMPACT).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Chien JC, Chiu T-C. Design optimization for wafer level package by using sequential optimization and reliability assessment method. In 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2016 - Proceedings. IEEE Computer Society. 2016. p. 184-187. 7800049. (Proceedings of Technical Papers - International Microsystems, Packaging, Assembly, and Circuits Technology Conference, IMPACT). https://doi.org/10.1109/IMPACT.2016.7800049