Design optimization for wafer level package reliability by using artificial neural network

P. C. Lai, Tz-Cheng Chiu, G. S. Shen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

An artificial neural network (ANN) based multi-objective design optimization for a wafer level package (WLP) is presented. Design factors including bump pad configuration, solder alloy composition, bump pad opening diameter, pad overhang (Cu pad radius minus pad opening radius), redistribution layer (RDL) polymer dielectric thickness and under-bump Cu thickness are grouped and considered by using a 3-level full factorial design of simulations (DoS) procedure. Key failure indices corresponding to solder joint fatigue fracture, RDL trace fatigue fracture and polymer dielectric cracking are selected as the objective functions for the design optimization. The Pareto optimal solutions are determined by using a genetic algorithm, and the compromise programming method is applied to determine the most reliable design.

Original languageEnglish
Title of host publication2013 8th International Microsystems, Packaging, Assembly and Circuits Technology Conference - Green and Cloud
Subtitle of host publicationCreating Value and Toward Eco-Life, IMPACT 2013 - Proceedings
Pages172-175
Number of pages4
DOIs
Publication statusPublished - 2013 Dec 1
Event2013 8th International Microsystems, Packaging, Assembly and Circuits Technology Conference - Green and Cloud: Creating Value and Toward Eco-Life, IMPACT 2013 - Taipei, Taiwan
Duration: 2013 Oct 222013 Oct 25

Publication series

NameProceedings of Technical Papers - International Microsystems, Packaging, Assembly, and Circuits Technology Conference, IMPACT
ISSN (Print)2150-5934
ISSN (Electronic)2150-5942

Other

Other2013 8th International Microsystems, Packaging, Assembly and Circuits Technology Conference - Green and Cloud: Creating Value and Toward Eco-Life, IMPACT 2013
Country/TerritoryTaiwan
CityTaipei
Period13-10-2213-10-25

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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