Design optimization in write speed of multi-level cell application for phase change memory

Jun Tin Lin, Yi Bo Liao, Meng Hsueh Chiang, I. Hsuan Chiu, Chia Long Lin, Wei Chou Hsu, Pei Chia Chiang, Shyh Shyuan Sheu, Yen Ya Hsu, Wen Hsing Liu, Keng Li Su, Ming Jer Kao, Ming Jinn Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

Design optimization to improve write speed of phase change memory is shown achievable by using a physical yet analytical compact PCM model. Our simulation results suggested that the write speed of continuous pulse programming scheme can be optimized and is superior to slow quenching scheme for multi-level cell application.

Original languageEnglish
Title of host publication2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009
Pages525-528
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009 - Xi'an, China
Duration: 2009 Dec 252009 Dec 27

Publication series

Name2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009

Other

Other2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009
CountryChina
CityXi'an
Period09-12-2509-12-27

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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