Design optimization in write speed of multi-level cell application for phase change memory

Jun Tin Lin, Yi Bo Liao, Meng-Hsueh Chiang, I. Hsuan Chiu, Chia Long Lin, Wei-Chou Hsu, Pei Chia Chiang, Shyh Shyuan Sheu, Yen Ya Hsu, Wen Hsing Liu, Keng Li Su, Ming Jer Kao, Ming Jinn Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

Design optimization to improve write speed of phase change memory is shown achievable by using a physical yet analytical compact PCM model. Our simulation results suggested that the write speed of continuous pulse programming scheme can be optimized and is superior to slow quenching scheme for multi-level cell application.

Original languageEnglish
Title of host publication2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009
Pages525-528
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009 - Xi'an, China
Duration: 2009 Dec 252009 Dec 27

Publication series

Name2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009

Other

Other2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009
CountryChina
CityXi'an
Period09-12-2509-12-27

Fingerprint

Phase change memory
Pulse code modulation
Quenching
Design optimization

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Lin, J. T., Liao, Y. B., Chiang, M-H., Chiu, I. H., Lin, C. L., Hsu, W-C., ... Tsai, M. J. (2009). Design optimization in write speed of multi-level cell application for phase change memory. In 2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009 (pp. 525-528). [5394196] (2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009). https://doi.org/10.1109/EDSSC.2009.5394196
Lin, Jun Tin ; Liao, Yi Bo ; Chiang, Meng-Hsueh ; Chiu, I. Hsuan ; Lin, Chia Long ; Hsu, Wei-Chou ; Chiang, Pei Chia ; Sheu, Shyh Shyuan ; Hsu, Yen Ya ; Liu, Wen Hsing ; Su, Keng Li ; Kao, Ming Jer ; Tsai, Ming Jinn. / Design optimization in write speed of multi-level cell application for phase change memory. 2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009. 2009. pp. 525-528 (2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009).
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abstract = "Design optimization to improve write speed of phase change memory is shown achievable by using a physical yet analytical compact PCM model. Our simulation results suggested that the write speed of continuous pulse programming scheme can be optimized and is superior to slow quenching scheme for multi-level cell application.",
author = "Lin, {Jun Tin} and Liao, {Yi Bo} and Meng-Hsueh Chiang and Chiu, {I. Hsuan} and Lin, {Chia Long} and Wei-Chou Hsu and Chiang, {Pei Chia} and Sheu, {Shyh Shyuan} and Hsu, {Yen Ya} and Liu, {Wen Hsing} and Su, {Keng Li} and Kao, {Ming Jer} and Tsai, {Ming Jinn}",
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language = "English",
isbn = "9781424442980",
series = "2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009",
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Lin, JT, Liao, YB, Chiang, M-H, Chiu, IH, Lin, CL, Hsu, W-C, Chiang, PC, Sheu, SS, Hsu, YY, Liu, WH, Su, KL, Kao, MJ & Tsai, MJ 2009, Design optimization in write speed of multi-level cell application for phase change memory. in 2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009., 5394196, 2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009, pp. 525-528, 2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009, Xi'an, China, 09-12-25. https://doi.org/10.1109/EDSSC.2009.5394196

Design optimization in write speed of multi-level cell application for phase change memory. / Lin, Jun Tin; Liao, Yi Bo; Chiang, Meng-Hsueh; Chiu, I. Hsuan; Lin, Chia Long; Hsu, Wei-Chou; Chiang, Pei Chia; Sheu, Shyh Shyuan; Hsu, Yen Ya; Liu, Wen Hsing; Su, Keng Li; Kao, Ming Jer; Tsai, Ming Jinn.

2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009. 2009. p. 525-528 5394196 (2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Lin JT, Liao YB, Chiang M-H, Chiu IH, Lin CL, Hsu W-C et al. Design optimization in write speed of multi-level cell application for phase change memory. In 2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009. 2009. p. 525-528. 5394196. (2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009). https://doi.org/10.1109/EDSSC.2009.5394196