Designing self-testable cellular arrays

Cheng Wen Wu, Shyue Kung Lu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

We present design-for-testability techniques and built-in self-test structures for cellular arrays based on the M-testability condition, which results in the minimal number of tests. Our technique applies to arrays with arbitrary dimensions and various connections. A systolic array multiplier is given as an example, showing an overhead of only 4% for making it M-testable. Our method compares favorably with that based on pI-testability. It reduces drastically the testing costs for circuits realized as cellular arrays.

Original languageEnglish
Title of host publicationIEEE International Conference on Computer Design - VLSI in Computers and Processors
PublisherPubl by IEEE
Pages110-113
Number of pages4
ISBN (Print)0818622709
Publication statusPublished - 1991 Dec 1
EventProceedings of the 1991 IEEE International Conference on Computer Design - VLSI in Computers and Processors - ICCD '91 - Cambridge, MA, USA
Duration: 1991 Oct 141991 Oct 16

Publication series

NameIEEE International Conference on Computer Design - VLSI in Computers and Processors

Conference

ConferenceProceedings of the 1991 IEEE International Conference on Computer Design - VLSI in Computers and Processors - ICCD '91
CityCambridge, MA, USA
Period91-10-1491-10-16

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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