A thermoelectric energy generator (TEG) is to convert the temperature difference between the hot and cold junctions into electrical energy by Seebeck effect. This work proposes a TEG design implemented by standard CMOS process to improve energy harvesting performance and to expedite the fabrication process. The TEG has double cavity with the upper cavity of 5.2μ m and the lower cavity of 10μ m in depth, which are created by dry etching post process for thermal isolation to improve energy conversion. The size and geometry of the thermocouples are determined to match their thermal/electrical resistance for optimal performance. A 5×5 mm2 TEG chip with four 2×2 mm2 cells, two in electrical series and another two in parallel, is implemented by CMOS process in semiconductor foundry service (TSMC D35 2P4M). Experiments validate that the voltage/power factor of the cells in the TEG chip agree very well. In simulation, the double cavity design achieves the performance 30% higher than that in previous work with only lower cavity. In experimental measurement, the TEG has voltage factor 2.889 V/cm2K and power factor 0.0450μ W /cm2K2. This is by far best TEG performance by matured, standard CMOS process in semiconductor foundry.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering