Device enhancement using process-strained-Si for sub-100-nm nMOSFET

Jen Pan Wang; Yan Kuin Su; Jone F. Chen

doi:10.1109/TED.2006.871874

Device enhancement using process-strained-Si for sub-100-nm nMOSFET

Jen Pan Wang, Yan Kuin Su, Jone F. Chen

Institute of Microelectronics

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

Process-induced strain using a high-tensile contact etch stop layer has demonstrated 18% transconductance and 18% driving current enhancement at a gate length/width of 80 nm/0.6μm for bulk nMOSFETs without degrading the device performance of pMOSFET. A superior current drive at 917μA/μm for nMOSFET is achieved with 1.7-nm gate oxide, 80-nm gate length, and 1.2-V operation voltage. The gate delay for an inverter ring oscillator is improved up to 13%.

Original language	English
Pages (from-to)	1276-1279
Number of pages	4
Journal	IEEE Transactions on Electron Devices
Volume	53
Issue number	5
DOIs	https://doi.org/10.1109/TED.2006.871874
Publication status	Published - 2006 May

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/TED.2006.871874

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title = "Device enhancement using process-strained-Si for sub-100-nm nMOSFET",

abstract = "Process-induced strain using a high-tensile contact etch stop layer has demonstrated 18% transconductance and 18% driving current enhancement at a gate length/width of 80 nm/0.6μm for bulk nMOSFETs without degrading the device performance of pMOSFET. A superior current drive at 917μA/μm for nMOSFET is achieved with 1.7-nm gate oxide, 80-nm gate length, and 1.2-V operation voltage. The gate delay for an inverter ring oscillator is improved up to 13%.",

author = "Wang, {Jen Pan} and Su, {Yan Kuin} and Chen, {Jone F.}",

year = "2006",

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AU - Su, Yan Kuin

AU - Chen, Jone F.

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N2 - Process-induced strain using a high-tensile contact etch stop layer has demonstrated 18% transconductance and 18% driving current enhancement at a gate length/width of 80 nm/0.6μm for bulk nMOSFETs without degrading the device performance of pMOSFET. A superior current drive at 917μA/μm for nMOSFET is achieved with 1.7-nm gate oxide, 80-nm gate length, and 1.2-V operation voltage. The gate delay for an inverter ring oscillator is improved up to 13%.

AB - Process-induced strain using a high-tensile contact etch stop layer has demonstrated 18% transconductance and 18% driving current enhancement at a gate length/width of 80 nm/0.6μm for bulk nMOSFETs without degrading the device performance of pMOSFET. A superior current drive at 917μA/μm for nMOSFET is achieved with 1.7-nm gate oxide, 80-nm gate length, and 1.2-V operation voltage. The gate delay for an inverter ring oscillator is improved up to 13%.

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JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

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Device enhancement using process-strained-Si for sub-100-nm nMOSFET

Abstract

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