Device enhancement using process-strained-Si for sub-100-nm nMOSFET

Jen Pan Wang, Yan Kuin Su, Jone-Fang Chen

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)

Abstract

Process-induced strain using a high-tensile contact etch stop layer has demonstrated 18% transconductance and 18% driving current enhancement at a gate length/width of 80 nm/0.6μm for bulk nMOSFETs without degrading the device performance of pMOSFET. A superior current drive at 917μA/μm for nMOSFET is achieved with 1.7-nm gate oxide, 80-nm gate length, and 1.2-V operation voltage. The gate delay for an inverter ring oscillator is improved up to 13%.

Original languageEnglish
Pages (from-to)1276-1279
Number of pages4
JournalIEEE Transactions on Electron Devices
Volume53
Issue number5
DOIs
Publication statusPublished - 2006 May 1

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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