DfT architecture for 3D-SICs with multiple towers

Chun Chuan Chi; Erik Jan Marinissen; Sandeep Kumar Goel; Cheng Wen Wu

doi:10.1109/ETS.2011.52

DfT architecture for 3D-SICs with multiple towers

Chun Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng Wen Wu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

33 Citations (Scopus)

Abstract

Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) provide attractive benefits such as smaller form factor, higher performance, and lower power. So far, prior work on Design-for-Testability (DfT) only focused on 3D-SICs consisting of a single "tower", i.e., a 3D-SIC in which each stack level contains exactly one die. 3D stacking technology allows to place multiple dies on top of a common base die, resulting in 3D-SICs with multiple "towers". This paper presents a generic DfT architecture for 3D-SICs having any number of "towers", possibly including "sub-towers". We also present efficient test control mechanisms. Experimental results show that the proposed architecture has a negligible area cost for medium-sized and larger industrial designs, and therefore provides a cost-effective test solution for 3D-SICs.

Original language	English
Title of host publication	Proceedings - 16th IEEE European Test Symposium, ETS 2011
Pages	51-56
Number of pages	6
DOIs	https://doi.org/10.1109/ETS.2011.52
Publication status	Published - 2011 Aug 29
Event	16th IEEE European Test Symposium, ETS 2011 - Trondheim, Norway Duration: 2011 May 23 → 2011 May 27

Publication series

Name	Proceedings - 16th IEEE European Test Symposium, ETS 2011

Conference

Conference	16th IEEE European Test Symposium, ETS 2011
Country/Territory	Norway
City	Trondheim
Period	11-05-23 → 11-05-27

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/ETS.2011.52

Cite this

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title = "DfT architecture for 3D-SICs with multiple towers",

abstract = "Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) provide attractive benefits such as smaller form factor, higher performance, and lower power. So far, prior work on Design-for-Testability (DfT) only focused on 3D-SICs consisting of a single {"}tower{"}, i.e., a 3D-SIC in which each stack level contains exactly one die. 3D stacking technology allows to place multiple dies on top of a common base die, resulting in 3D-SICs with multiple {"}towers{"}. This paper presents a generic DfT architecture for 3D-SICs having any number of {"}towers{"}, possibly including {"}sub-towers{"}. We also present efficient test control mechanisms. Experimental results show that the proposed architecture has a negligible area cost for medium-sized and larger industrial designs, and therefore provides a cost-effective test solution for 3D-SICs.",

author = "Chi, {Chun Chuan} and Marinissen, {Erik Jan} and Goel, {Sandeep Kumar} and Wu, {Cheng Wen}",

year = "2011",

month = aug,

day = "29",

doi = "10.1109/ETS.2011.52",

language = "English",

isbn = "9780769544335",

series = "Proceedings - 16th IEEE European Test Symposium, ETS 2011",

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note = "16th IEEE European Test Symposium, ETS 2011 ; Conference date: 23-05-2011 Through 27-05-2011",

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AU - Chi, Chun Chuan

AU - Marinissen, Erik Jan

AU - Goel, Sandeep Kumar

AU - Wu, Cheng Wen

PY - 2011/8/29

Y1 - 2011/8/29

N2 - Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) provide attractive benefits such as smaller form factor, higher performance, and lower power. So far, prior work on Design-for-Testability (DfT) only focused on 3D-SICs consisting of a single "tower", i.e., a 3D-SIC in which each stack level contains exactly one die. 3D stacking technology allows to place multiple dies on top of a common base die, resulting in 3D-SICs with multiple "towers". This paper presents a generic DfT architecture for 3D-SICs having any number of "towers", possibly including "sub-towers". We also present efficient test control mechanisms. Experimental results show that the proposed architecture has a negligible area cost for medium-sized and larger industrial designs, and therefore provides a cost-effective test solution for 3D-SICs.

AB - Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) provide attractive benefits such as smaller form factor, higher performance, and lower power. So far, prior work on Design-for-Testability (DfT) only focused on 3D-SICs consisting of a single "tower", i.e., a 3D-SIC in which each stack level contains exactly one die. 3D stacking technology allows to place multiple dies on top of a common base die, resulting in 3D-SICs with multiple "towers". This paper presents a generic DfT architecture for 3D-SICs having any number of "towers", possibly including "sub-towers". We also present efficient test control mechanisms. Experimental results show that the proposed architecture has a negligible area cost for medium-sized and larger industrial designs, and therefore provides a cost-effective test solution for 3D-SICs.

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M3 - Conference contribution

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BT - Proceedings - 16th IEEE European Test Symposium, ETS 2011

T2 - 16th IEEE European Test Symposium, ETS 2011

Y2 - 23 May 2011 through 27 May 2011

ER -

DfT architecture for 3D-SICs with multiple towers

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