DfT architecture for 3D-SICs with multiple towers

Chun Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

31 Citations (Scopus)


Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) provide attractive benefits such as smaller form factor, higher performance, and lower power. So far, prior work on Design-for-Testability (DfT) only focused on 3D-SICs consisting of a single "tower", i.e., a 3D-SIC in which each stack level contains exactly one die. 3D stacking technology allows to place multiple dies on top of a common base die, resulting in 3D-SICs with multiple "towers". This paper presents a generic DfT architecture for 3D-SICs having any number of "towers", possibly including "sub-towers". We also present efficient test control mechanisms. Experimental results show that the proposed architecture has a negligible area cost for medium-sized and larger industrial designs, and therefore provides a cost-effective test solution for 3D-SICs.

Original languageEnglish
Title of host publicationProceedings - 16th IEEE European Test Symposium, ETS 2011
Number of pages6
Publication statusPublished - 2011 Aug 29
Event16th IEEE European Test Symposium, ETS 2011 - Trondheim, Norway
Duration: 2011 May 232011 May 27

Publication series

NameProceedings - 16th IEEE European Test Symposium, ETS 2011


Conference16th IEEE European Test Symposium, ETS 2011

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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