@inproceedings{5b6843faf056466293dc5b14940e9ca6,
title = "Diagnosing Transition Delay Faults under Scan-Based Logic Array",
abstract = "This paper presents a novel diagnostic procedure for transition delay faults (TDFs) using a two-dimensional scan - based test chip architecture. The test chip architecture consists of C-testable blocks (CTBs) and scan registers. Each CTB has the distinguished VH-bijection property that ensures any change on either the vertical or horizontal input of a CTB will lead to changes in both vertical and horizontal outputs. The diagnostic procedure consists of two tests, one for the scan chain test and the other for the whole chip test. Experimental result s show that the required time for a test chip containing 68∗68 8-input/8-output CTBs is less than 0.2 seconds when executing the test procedure at 100MHz. The proposed diagnostic procedure can achieve 100% diagnosability for all transition faults in th e test chip.",
author = "Kang, {Duo Yao} and Lin, {Shiou Ning} and Lee, {Kuen Jong}",
note = "Funding Information: This work was supported in part by the Ministry of Science and Technology of Taiwan under Contract 109-2218-E-006-025. Publisher Copyright: {\textcopyright} 2022 IEEE.; 6th IEEE International Test Conference in Asia, ITC-Asia 2022 ; Conference date: 24-08-2022 Through 26-08-2022",
year = "2022",
doi = "10.1109/ITCAsia55616.2022.00013",
language = "English",
series = "Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "13--18",
booktitle = "Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022",
address = "United States",
}